16-Bit Latchup Protected
Analog to Digital Converter
7809LP
R/C
CS
POWER DOWN
Successive Approximation Register and Control Logic
Clock
CDAC
20 kΩ
R1
IN
10 kΩ
R2
IN
5 kΩ
R3
IN
20 kΩ
Comparator
Serial Data
Out
Data
Clock
Serial
Data
BUSY
CAP
Buffer
4 kΩ
REF
Internal
+2.5V Ref.
Memory
Logic Diagram
F
EATURES
:
• R
AD
-P
AK
® radiation-hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Latch-up Protection Technology (LPT
TM
)
• SEL converted into a reset
- Rate based on cross section and mission
• Same footprint as ADS7809
• Package: 24 pin R
AD
-P
AK
flat package
• 100 kHz min sampling rate
• ±10 V and 0 V to 5 V input range
• Advanced CMOS technology
• DNL: 16-bits “No Missing Codes”
• 83 dB min SINAD with 20 kHz input
• Single +5 V supply operation
• Utilizes internal or external reference
• Serial output
• Power dissipation: 132 mW max
D
ESCRIPTION
:
Maxwell Technologies’ 7809LP high-speed 16-bit analog to
digital converter features a greater than 100 kilorad (Si) total
dose tolerance depending upon space mission. Using Max-
well’s radiation-hardened R
AD
-P
AK
® packaging technology, the
7809LP has the same footprint as ADS7809 and is latchup
protected by Maxwell Technologies’ Latchup Protection Tech-
nology (LPT
TM
). It is a 24 pin, 16-bit sampling analog-to-digital
converter using state-of-the-art CMOS structures. The
7809LP contains a 16-bit capacitor based SAR A/D with S/H,
reference, clock, interface for microprocessor use, and serial
output drivers. The 7809LP is specified at a 100kHz sampling
rate, and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide various input ranges include
±10 V and 0 to 5 V, while the innovative design allows opera-
tion from a single +5 V supply, with power dissipation of under
132 mW.
Maxwell Technologies' patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class K.
02.28.02 Rev 5
All data sheets are subject to change without notice
1
(858) 503-3300- Fax: (858) 503-3301 - www.maxwell.com
©2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
T
ABLE
1. 7809LP P
IN
D
ESCRIPTION
P
IN
1
2
3
4
5
6
7
8
S
YMBOL
R1IN
AGND1
R2IN
R3IN
CAP
REF
AGND2
SB/BTC
Analog Input.
Analog Ground. Used internally as ground reference point.
Analog Input.
Analog Input.
Reference Buffer Capacitor. 2.2 µF tantalum to ground.
Reference Input/Output. 2.2 µF tantalum capacitor to ground.
Analog Ground.
D
ESCRIPTION
7809LP
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be
output in a Straight Binary format. If LOW, data will be output in a Binary Two’s Complement
format.
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized
to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the
data from the previous conversion, along with 16 clock pulses output on DATACLK.
Digital Ground.
Built In test function of the latchup protection. Drive LOW during normal operation.
9
EXT/INT
Memory
10
11
12
13
14
15
16
DGND
LPBIT
LPSTATUS Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is
active and output data is invalid.
VANA
VDIG
SYNC
DATACLK
Analog Supply Input. Nominally 5V.
Digital Supply Input. Nominally 5V.
Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on
CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK.
Either an input or an output depending on the EXT/INT level. Output data will be synchronized
to this clock. If EXT/INT is LOW, DATACLK will transmit 16 pulses after each conversion, and
then remain LOW between conversions.
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the
level of SB/BTC. In the external clock mode, after 16-bits of data, the 7809LOPO will output the
level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid
on both the rising and falling edges of DATACLK, and between conversions DATA will stay at
the level of the TAG input when the conversion was started.
Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data input on TAG will
be output on DATA with a delay of 16 DATACLK pulses as long as CS is LOW and R/C is
HIGH.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the
hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission
of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with
CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the
transmission of data from the previous conversion.
Chip Select. Internally OR’ed with R/C.
17
DATA
18
TAG
19
R/C
20
CS
02.28.02 Rev 5
All data sheets are subject to change without notice
2
©2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
T
ABLE
1. 7809LP P
IN
D
ESCRIPTION
P
IN
21
S
YMBOL
BUSY
D
ESCRIPTION
7809LP
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is com-
pleted and the data is latched into the output shift register. CS or R/C must be HIGH when
BUSY rises, or another conversion will start without time for signal acquisition.
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversions are maintained in the output shift register.
Latchup Protection Analog Supply.
Latchup Protection Digital Supply.
22
23
24
PWRD
LPVANA
LPVDIG
T
ABLE
2. 7809LP A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Analog Inputs
S
YMBOL
R1
IN
R2
IN
R3
IN
CAP
REF
1
M
IN
-25
-25
-25
V
ANA
+ 0.3
-0.3
--
--
-40
-0.3
T
STG
-65
M
AX
25
25
25
AGND2 - 0.3
0.3
7
7
0.3
85
V
DIG
+ 0.3
150
U
NIT
V
V
V
V
V
V
V
V
°
C
Memory
Ground Voltage Differences: DGND, AGND2
V
ANA
V
DIG
V
DIG
to V
ANA
Operating Temperature
Digital Inputs
Storage Temperature
1. Indefinite short to AGND2, momentarily short to V
ANA
.
V
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
Icc
V
ARIATIONS
+/- 10%
T
ABLE
4. 7809LP DC A
CCURACY
S
PECIFICATIONS
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Integral Linearity Error
+ 25°C
-40 to 85°C
Differential Linearity Error
+ 25°C
-40 to 85°C
S
UBGROUPS
1
2, 3
1
2, 3
02.28.02 Rev 5
M
IN
--
--
--
--
T
YP
--
--
--
--
M
AX
±3
±5
-2, 3
-1, 6
U
NIT
LSB
1
LSB
LSB
All data sheets are subject to change without notice
3
©2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
T
ABLE
4. 7809LP DC A
CCURACY
S
PECIFICATIONS
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
No Missing Codes
2
Transition Noise
3
Full Scale Error
4,5
Full Scale Error
4,5
(using ext. 2.5000 V
ref
)
Full Scale Error Drift
Full Scale Error Drift (using ext. 2.5000 V
ref
)
Bipolar Zero Error
4
Bipolar Zero Error Drift
Unipolar Zero Error
4
+ 25°C
-40 to 85°C
Unipolar Zero Error Drift
Recovery to Rated Accuracy after Power Down (1 uF Capacitor to
CAP)
Power Supply Sensitivity (V
DIG
= V
ANA
= V
D
) 4.75 V > V
D
< 5.2 V
+ 25°C
-40 to 85°C
1. LSB stands for Least Significant Bit. One LSB is equal to 305 µV.
2. Not tested.
3. Typical rms noise at worst case transitions and temperatures.
4. Measured with various fixed resistors.
1
2, 3
1
2, 3
1, 2, 3
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
M
IN
15
--
--
--
--
--
--
--
--
--
--
--
±7
±2
--
±2
--
--
±2
1
T
YP
--
1.3
--
7809LP
M
AX
--
--
±0.6
±0.6
--
--
±10
--
±3
±16
--
--
U
NIT
Bits
LSB
%
%
ppm/
°
C
ppm/
°
C
mV
ppm/
°
C
mV
mV
ppm/
°
C
ms
LSB
LSB
Memory
--
--
--
--
±8
±32
5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last scale code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error.
T
ABLE
5. 7809LP D
IGITAL
I
NPUTS
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
V
IL
V
IH
I
IL
, I
IH
1, 2, 3
1, 2, 3
1, 2, 3
M
IN
-0.3
2.0
--
T
YP
--
--
--
M
AX
0.8
V
D
+ 0.3
±10
U
NIT
V
V
µA
T
ABLE
6. 7809LP A
NALOG
I
NPUT AND
T
HROUGHPUT
S
PEED
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Voltage Ranges
Impedance
02.28.02 Rev 5
S
UBGROUPS
M
IN
T
YP
M
AX
U
NIT
10 V, 0 V to 5 V
See Table 2.
All data sheets are subject to change without notice
4
©2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected Analog to Digital Converter
T
ABLE
6. 7809LP A
NALOG
I
NPUT AND
T
HROUGHPUT
S
PEED
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Capacitance
Conversion Time
Complete Cycle (Acquire and Convert)
Throughput Rate
1
1. Tested by application of signal.
9, 10, 11
9, 10, 11
S
UBGROUPS
M
IN
--
--
--
100
T
YP
35
7.6
--
--
7809LP
M
AX
--
8
10
--
U
NIT
pF
µs
µs
kHz
T
ABLE
7. 7809LP AC A
CCURACY
S
PECIFICATIONS
1
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Spurious-Free Dynamic Range, f
IN
= 20 kHz
1
Total Harmonic Distortion, f
IN
= 20 kHz
1
Signal-to-Noise (Noise + Distortion)
1
f
IN
= 20 kHz
-60 dB Input
Signal-to-Noise
1
, f
IN
= 20 kHz
Full-Power Bandwidth
1,3
1. Guaranteed by design.
2. All specifications in dB are referred to a full-scale ±10 V input.
3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB.
S
UBGROUPS
M
IN
90
--
83
--
83
--
T
YP
100
-100
88
30
88
250
M
AX
--
-90
--
--
--
--
dB
kHz
U
NIT
dB
2
dB
Memory
dB
T
ABLE
8. 7809LP S
AMPLING
D
YNAMICS
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Aperture Delay
Aperture Jitter
Transient Response FS Step
Overvoltage Recovery
1
1. Recovers to specified performance after 2 X FS input overvoltage.
--
--
M
IN
--
T
YP
40
2
150
M
AX
--
--
--
U
NIT
ns
us
ns
Sufficient to meet AC specification
T
ABLE
9. 7809LP R
EFERENCE
(S
PECIFIED
P
ERFORMANCE
-40
TO
+85°C)
P
ARAMETER
Internal Reference Voltage
C
ONDITIONS
No Load
S
UBGROUPS
1, 2, 3
02.28.02 Rev 5
M
IN
2.48
T
YP
2.5
M
AX
2.52
U
NIT
V
All data sheets are subject to change without notice
5
©2001 Maxwell Technologies
All rights reserved.
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