72SD3232
1 Gbit SDRAM
32-Meg X 32-Bit X 4-Banks
Logic Diagram
(One Amplifier)
Memory
F
EATURES
:
• 1 Gigabit ( 32-Meg X 32-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
SEL
TH
> 85 MeV/mg/cm
2
@ 25
°
C
D
ESCRIPTION
:
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 1 Gigabits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
SRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time, and the ability to randomly change column
address during each clock cycle.
Maxwell Technologies’ patented R
AD
-P
AK
®
packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, R
AD
-P
AK
®
provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
01.11.05 Rev 2
•
•
•
•
•
•
•
•
•
•
JEDEC Standard 3.3V Power Supply
Clock Frequency: 100 MHz Operation
Operating tremperature: -55 to +125
°
C
Auto Refresh
Single pulsed RAS
2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
Programmable CAS latency: 2/3
Power Down and Clock Suspend Modes
LVTTL Compatible Inputs and Outputs
Package: 72-Pin R
AD
-Stack Package
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
72SD3232
Pinout Description
Pin Descriptions
Pin Name
A0 to A12
BA0, BA1
Address Input
Row Address A0 to A12
Column Address A0 to A9
Bank Select Address BA0/BA1 (BS)
DQ0 to DQ7
DQ8 to DQ15
DQ16 to DQ23
DQ24 to DQ32
CS\
RAS\
CAS\
WE\
DQM 1
DQM 2
DQM 3
DQM 4
CLK1
CLK2
CKE
Vcc
Vss
VccQ
VssQ
NC
Data-Input/Output - Layer 1
Data-Input/Output - Layer 2
Function
Memory
Data-Input/Output - Layer 3
Data-Input/Output - Layer 4
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Input/Output Mask - Layer 1
Input/Output Mask - Layer 2
Input/Output Mask - Layer 3
Input/Output Mask - Layer 4
Clock Input - Layer 1 & 3
Clock Input - Layer 2 & 4
Clock Enable
Power for internal circuits
Ground for internal circuits
Power for DQ circuits
Ground for DQ circuits
No Connection
72SD3232
01.11.05 Rev 2
All data sheets are subject to change without notice
2
©2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
‘
72SD3232
T
ABLE
1. A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on any pin relative to V
SS
Supply voltage relative to V
SS
Short circuit output current
Power Dissipation
Operating Temperature
Storage Temperature
S
YMBOL
V
IN
V
OUT
V
CC
I
OUT
P
D
T
OPR
T
STG
M
AX
-0.5 to VCC + 0.5
(< 4.6(max))
-0.5 to +4.6
50
1.0
-55 to +125
-65 to +150
U
NIT
V
V
mA
W
°C
°C
T
ABLE
2. R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
CC
Memory
P
ARAMETER
Supply Voltage
S
YMBOL
M
IN
M
AX
1,2
V
CC
, V
CCQ
3.0
3.6
3
V
SS
, V
SSQ
0
0
1,4
Input High Voltage
V
IH
2.0
V
CC
+ 0.3
1,5
Input Low Voltage
V
IL
-0.3
.8
1. All voltage referred to VSS
2. The supply voltage with all
V
CC
and V
CCQ
pins must be on the same level
3. The supply voltage with all V
SS
and V
SSQ
pins must be on the same level
4.
5.
V
IH
(max) =
V
CC
+2.0V for pulse width
<3ns
at
V
CC
V
IL
(min) =
V
SS
-2.0V for pulse width
<3ns
at
V
SS
U
NIT
V
V
V
V
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
1.
±10% of value specified in Table 4
D
ESCRIPTION
Operating Current
Standby Current in Power Down
Active Standby Current
V
ARIATION1
+ 10%
+ 10%
+ 10%
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Operating Current
1,2,3
S
YMBOL
I
CC1
T
EST
C
ONDITIONS
Burst length CAS Latency = 2
=1
CAS Latency = 3
t
RC
= min
CKE = V
IL
t
CK
= 12 ns
01.11.05 Rev 2
S
UBGROUPS
1, 2, 3
M
IN
M
AX
460
460
U
NITS
mA
Standby Current in Power Down
4
I
CC2P
1, 2, 3
12
mA
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
T
ABLE
4. DC E
LECTRICAL
C
HARACTERISTICS
72SD3232
S
UBGROUPS
1, 2, 3
M
IN
M
AX
8
U
NITS
mA
(V
CC
= 3.3V + 0.3V, V
CC
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Standby Current in Power Down
( input signal stable)
5
Standby Current in non power down
6
Standby Current in non power down
( Input signal stable)
7
Active standby current in
power down
1,2,4
Active standby current in power down
(input signal stable)
2,5
Active standby power in non power
down
1,2,6
Active standby current in non power
down ( input signal stable)
2,7
Burst Operating Current
1,2,8
CAS Latency = 2
CAS Latency = 3
Refresh Current
3
Self Refresh current
9
Input Leakage Current - CLK 1 & 2
Input Leakage Current - All Other
Output Leakage Current
Output high voltage
S
YMBOL
I
CC2PS
T
EST
C
ONDITIONS
CKE = V
IL
t
CK
= 0
CKE, CS = V
IH
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
CKE = V
IL
t
CK
= 12 ns
CKE = V
IL
t
CK
= 0
CKE, CS = V
IN
t
CK
= 12 ns
CKE = V
IH
t
CK
= 0
t
CK
= min
BL = 4
t
RC
= min
V
IH
>V
CC
- 0.2V
V
IL
< 0.2 V
0<V
IN
<V
CC
0<V
IN
<V
CC
0<VOUT<V
CC
I
OH
= -4mA
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
80
36
16
12
120
60
mA
mA
mA
mA
mA
mA
Memory
mA
440
580
I
CC5
I
CC6
I
LI
I
LI
I
LO
V
OH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-2
-4
-1.5
2.4
880
12
4
4
1.5
mA
mA
uA
uA
uA
V
I
OL
= 4 mA
1, 2, 3
0.4
V
Output low voltage
V
OL
1. ICC1 depends on output load conditions when the device is selected. ICC(max) is specified with the output open.
2. One Bank operation.
3. Input signals are changed once per one clock.
4. After power down mode, CLK operating current.
5. Afer power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals are VIH or VIL fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Use self reset only at temperatures below 70°C
01.11.05 Rev 2
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.
1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM
T
ABLE
5. AC Electrical Characteristics
72SD3232
M
IN
10
7.5
T
YP
M
AX
U
NIT
ns
(V
DD
=3.3V + 0.3V, V
DD
Q = 3.3V + 0.3V, T
A
= -55
TO
125°C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
System clock cycle time
1
(CAS latency = 2)
(CAS latency = 3)
CLK high pulse width
1,7
CLK low pulse width
1,7
Access time from CLK
1,2
(CAS latency = 2)
(CAS latency = 3)
Data-out hold time
1,2
CLK to Data-out low impedance
1,2,3,7
CLK to Data-out high impedance
1,4,7
(CAS latency = 2, 3)
Input setup time
1,5,6
CKE setup time for power down exit
1
Input hold time
1,6
Ref/Active to Ref/Active command period
1
Active to Precharge command period
1
Active command to column command
(same bank)
1
Precharge to Active command period
1
Write recovery or data-in to precharge
lead time
1
Active( a) to Active (b) command period
Transition time(rise and fall)
7
Refresh Period
S
YMBOL
t
CK
S
UBGROUPS
9, 10, 11
t
CKH
t
CKL
t
AC
9, 10, 11
9, 10, 11
9, 10, 11
2.5
2.5
6
6
ns
ns
ns
t
OH
t
LZ
t
HZ
t
AS
, t
CS,
t
DS
, t
CES
t
CESP
t
AH
, t
CH
, t
DH
t
CEH
t
RC
t
RAS
t
RCD
t
RP
t
DPL
t
RRD
t
T
t
REF
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
105°C
85°C
2.7
2
5.4
1.5
1.5
1.5
70
50
20
20
20
20
1
16
32
64
5
6.4
16
8
120000
ns
ns
ns
ns
Memory
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
70°C
128
1. AC measurement assumes t
T
=1ns. Reference level for timing of input signals is 1.5V
2. Access time is measured at 1.5V.
3. t
LZ
(min) defines the time at which the outputs achieve the low impedance state.
4. t
HZ
(min) defines the time at which the outputs achieve the high impedance state.
5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.
6. t
AS
/t
AH
: Address, tC/tCH: /CS, /RAS, /CAS, /WE, DQM
7. Guarenteed by design. (Not Tested)
8. Guarenteed by Device Characterization. ( Not 100% Tested)
01.11.05 Rev 2
All data sheets are subject to change without notice
5
©2005 Maxwell Technologies
All rights reserved.
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