74LV02
Quad 2-input NOR gate
Rev. 04 — 20 December 2007
Product data sheet
1. General description
The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC02 and 74HCT02.
The 74LV02 provides a quad 2-input NOR function.
2. Features
s
s
s
s
s
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV02D
74LV02PW
74LV02BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74LV02
Quad 2-input NOR gate
4. Functional diagram
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
1Y
1
2
≥1
1
A
≥1
4
B
Y
mna215
2Y
4
3
5
3Y
10
6
8
9
11
12
4Y
13
≥1
10
mna216
≥1
13
001aah084
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LV02
terminal 1
index area
1A
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
001aac919
2
3
4
5
6
7
GND
3A
8
V
CC(1)
14 V
CC
13 4Y
12 4B
11 4A
10 3Y
9
3B
14 V
CC
13 4Y
12 4B
1B
2Y
2A
2B
02
11 4A
10 3Y
9
8
3B
3A
1
1Y
001aah093
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
1A
1B
74LV02_4
Pin description
Pin
1
2
3
Description
data output
data input
data input
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 20 December 2007
2 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
Table 2.
Symbol
2Y
2A
2B
GND
3A
3B
3Y
4A
4B
4Y
V
CC
Pin description
…continued
Pin
4
5
6
7
8
9
10
11
12
13
14
Description
data output
data input
data input
ground (0 V)
data input
data input
data output
data input
data input
data output
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input nA
L
X
H
Input nB
L
H
X
Output nY
H
L
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14 package
TSSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
Max
+7.0
±20
±50
±25
50
-
+150
500
500
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
74LV02_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 20 December 2007
3 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.2 V
I
O
=
−100 µA;
V
CC
= 2.0 V
I
O
=
−100 µA;
V
CC
= 2.7 V
I
O
=
−100 µA;
V
CC
= 3.0 V
I
O
=
−100 µA;
V
CC
= 4.5 V
I
O
=
−6
mA; V
CC
= 3.0 V
I
O
=
−12
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
C
C
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
-
-
-
-
0.3V
CC
V
74LV02_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 20 December 2007
4 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OL
LOW-level output voltage
Conditions
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.2 V
I
O
= 100
µA;
V
CC
= 2.0 V
I
O
= 100
µA;
V
CC
= 2.7 V
I
O
= 100
µA;
V
CC
= 3.0 V
I
O
= 100
µA;
V
CC
= 4.5 V
I
O
= 6 mA; V
CC
= 3.0 V
I
O
= 12 mA; V
CC
= 4.5 V
I
I
I
CC
∆I
CC
C
I
[1]
−40 °C
to +85
°C
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
[1]
0
0
0
0
0
0.25
0.35
-
-
-
3.5
Max
-
0.2
0.2
0.2
0.2
0.40
0.55
1.0
20.0
500
-
−40 °C
to +125
°C
Unit
Min
-
-
-
-
-
-
-
-
-
-
-
Max
-
0.2
0.2
0.2
0.2
0.50
0.65
1.0
40
850
-
V
V
V
V
V
V
V
µA
µA
µA
pF
input leakage current
supply current
additional supply current
input capacitance
V
I
= V
CC
or GND; V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input; V
I
= V
CC
−
0.6 V;
V
CC
= 2.7 V to 3.6 V
Typical values are measured at T
amb
= 25
°C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol Parameter
t
pd
propagation delay
Conditions
nA, nB to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V; C
L
= 15 pF
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[3]
[3]
[3]
[4]
[2]
−40 °C
to +85
°C
Min
-
-
-
-
-
-
-
Typ
[1]
40
14
10
6.0
7.5
6.0
22
Max
-
21
15
-
12
10
-
−40 °C
to +125
°C
Min
-
-
-
-
-
-
-
Max
-
26
19
-
15
13
-
Unit
ns
ns
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
All typical values are measured at T
amb
= 25
°C.
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz, f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
N = number of inputs switching
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
74LV02_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 20 December 2007
5 of 12
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