74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
Rev. 2 — 10 September 2020
Product data sheet
1. General description
The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
Input levels:
•
For 74HC27-Q100: CMOS level
•
For 74HCT27-Q100: TTL level
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC27D-Q100
74HCT27D-Q100
74HC27PW-Q100
74HCT27PW-Q100
74HC27BQ-Q100
74HCT27BQ-Q100
-40 °C to +125 °C
-40 °C to +125 °C
TSSOP14
-40 °C to +125 °C
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia
74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
4. Functional diagram
1
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
mna936
2
≥1
12
1Y
12
13
3
≥1
2Y
6
4
5
9
6
3Y
8
10
11
≥1
A
8
B
C
Y
mna937
mna935
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74HC27
74HCT27
terminal 1
index area
14 V
CC
1A
2
3
4
5
6
7
GND
3Y
8
GND
(1)
1
74HC27
74HCT27
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
001aag759
1B
2A
2B
13 1C
12 1Y
11 3C
10 3B
9
3A
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9
8
3A
3Y
2C
2Y
aaa-007685
Transparent top view
Fig. 4.
Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A
1B, 2B, 3B
1C, 2C, 3C
1Y, 2Y, 3Y
GND
V
CC
Pin
1, 3, 9
2, 4, 10
13, 5, 11
12, 6, 8
7
14
Description
data input
data input
data input
data output
ground (0 V)
supply voltage
74HC_HCT27_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 10 September 2020
2 / 12
Nexperia
74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Inputs
nA
L
X
X
H
nB
L
X
H
X
nC
L
H
X
X
Outputs
nY
H
L
L
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
[2]
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: P
tot
derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC27-Q100
Min
2.0
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT27-Q100
Min
4.5
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT27_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 10 September 2020
3 / 12
Nexperia
74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC27-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
V
I
= V
IH
or V
IL
HIGH-level
output voltage
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
V
I
= V
IH
or V
IL
LOW-level
output voltage
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND; V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1.0
20
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
40
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
Conditions
Min
25 °C
Typ
Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
3.98 4.32
5.48 5.81
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
74HCT27-Q100
V
IH
V
IL
V
OH
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
HIGH-level
output voltage
I
O
= -20 μA
I
O
= -4.0 mA
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
LOW-level
output voltage
I
O
= 20 μA
I
O
= 4.0 mA
input leakage
current
V
I
= V
CC
or GND; V
CC
= 5.5 V
4.4
4.5
-
-
0.1
0.26
±0.1
2.0
4.4
3.84
-
-
-
-
-
-
0.1
0.33
±1.0
20
4.4
3.7
-
-
-
-
-
-
0.1
0.4
±1.0
40
V
V
V
V
μA
μA
3.98 4.32
-
-
-
-
0
0.16
-
-
V
OL
I
I
I
CC
supply current V
I
= V
CC
or GND; V
CC
= 5.5 V;
I
O
= 0 A
74HC_HCT27_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 10 September 2020
4 / 12
Nexperia
74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
Conditions
Min
25 °C
Typ
Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
Symbol Parameter
ΔI
CC
per input pin; V
I
= V
CC
- 2.1 V;
additional
supply current other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V; I
O
= 0 A
nA, nB or nC inputs
-
-
150
3.5
540
-
-
-
675
-
-
-
735
-
μA
pF
input
capacitance
C
I
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit see
Fig. 7.
Symbol Parameter
74HC27-Q100
t
pd
propagation
delay
nA, nB, nC to nY;
see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation per package;
capacitance
V
I
= GND to V
CC
propagation
delay
nA, nB, nC to nY;
see
Fig. 6
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
C
PD
[1]
[2]
[3]
Conditions
Min
[1]
-
-
-
-
[2]
-
-
-
[3]
-
25 °C
Typ Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
28
10
8
8
19
7
6
24
90
18
-
15
75
15
13
-
-
-
-
-
-
-
-
-
115
23
-
20
95
19
16
-
-
-
-
-
-
-
-
-
135
27
-
23
110
22
19
-
ns
ns
ns
ns
ns
ns
ns
pF
74HCT27-Q100
t
pd
[1]
-
-
[2]
[3]
-
-
12
10
7
30
21
-
15
-
-
-
-
-
26
-
19
-
-
-
-
-
32
-
22
-
ns
ns
ns
pF
transition time
V
CC
= 4.5 V; see
Fig. 6
power dissipation per package;
capacitance
V
I
= GND to V
CC
- 1.5 V
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW):
2
2
P
D
= C
PD
x V
CC
x f
i
x N + Σ(C
L
x V
CC
x f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
2
Σ(C
L
x V
CC
x f
o
) = sum of outputs.
74HC_HCT27_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 10 September 2020
5 / 12
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
