Philips Semiconductors
Product specification
Quad 2-input OR gate
FEATURES
•
5 V tolerant inputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74LVC32AD
74LVC32ADB
74LVC32APW
74LVC32ABQ
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
14
14
14
14
PACKAGE
SO14
SSOP14
TSSOP14
DHVQFN14
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
DESCRIPTION
74LVC32A
The 74LVC32A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC32A provides the 2-input OR function.
TYPICAL
2.1
4.0
15
ns
pF
pF
UNIT
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT337-1
SOT402-1
SOT762-1
2003 Jul 16
2
Philips Semiconductors
Product specification
Quad 2-input OR gate
74LVC32A
handbook, halfpage
handbook, halfpage
1A
1
VCC
14
13
12
4B
4A
4Y
3B
3A
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
MNA240
14 VCC
13 4B
12 4A
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
32
11 4Y
10 3B
9
3A
GND
(1)
11
10
9
8 3Y
MNB060
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
1
2
≥
1
3
handbook, halfpage
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
≥
1
2Y
6
6
5
3Y
8
9
10
≥
1
8
4Y
11
12
MNA242
≥
1
11
13
MNA243
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2003 Jul 16
4
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