74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 06 — 4 June 2007
Product data sheet
1. General description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs,
clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
I
I
I
I
I
I
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
N
HBM JESD22-A114D exceeds 2000 V
N
CDM JESD22-C101C exceeds 1000 V
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to 125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC74AD
74LVC74ADB
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
74LVC74APW
−40 °C
to +125
°C
74LVC74ABQ
−40 °C
to +125
°C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
4. Functional diagram
1SD
SD
D
CP
FF
Q
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
Q
1Q
2Q
5
9
4
3
2
1
S
C1
1D
R
12
S
C1
1D
R
mna419
4
2
3
1D
1CP
Q
1Q
5
1Q
6
RD
5
1
6
10
1RD
2SD
SD
D
CP
FF
8
RD
13
2RD
mna420
2D
2CP
FF
Q
10
1Q
2Q
6
8
11
12
13
mna418
Q
2Q
9
9
11
RD
1RD 2RD
1 13
Q
2Q
8
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 4. Logic diagram for one flip-flop
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
2 of 16
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
1RD
2
3
4
5
6
7
GND
2Q
8
1
1D
1CP
1SD
1Q
1Q
GND
2
3
4
5
6
7
001aad106
1RD
1
14 V
CC
13 2RD
12 2D
terminal 1
index area
1D
1CP
1SD
1Q
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
2Q
74
11 2CP
10 2SD
74
GND
(1)
1Q
9
8
2Q
2Q
001aad107
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration for SO14 and (T)SSOP14
Fig 6. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
complement output
true output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
3 of 16
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
[1]
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 4.
Input
nSD
H
H
[1]
Function table
[1]
Output
nRD
H
H
nCP
↑
↑
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level
L = LOW voltage level
↑
= LOW-to-HIGH transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
X = don’t care
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[2]
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
4 of 16
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
8. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
o
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 1.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
for maximum speed performance
for low-voltage applications
Min
2.7
1.2
0
0
−40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
3.6
5.5
V
CC
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output
voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 1.2 V
V
CC
= 2.7 V to 3.6 V
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 2.7 V to 3.6 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−18
mA; V
CC
= 3.0 V
I
O
=
−24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 2.7 V to 3.6 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
CC
∆I
CC
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND
current
supply
current
additional
supply
current
input
capacitance
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
−
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
-
-
-
-
-
-
-
-
-
±0.1
0.1
5
0.2
0.4
0.55
±5
10
500
-
-
-
-
-
-
0.3
0.6
0.8
±20
40
5000
V
V
V
µA
µA
µA
V
CC
−
0.2
2.2
2.4
2.2
-
-
-
-
-
-
-
V
CC
−
0.3
2.05
2.25
2.0
-
-
-
-
V
V
V
V
−40 °C
to +85
°C
Min
V
CC
2.0
-
-
Typ
[1]
-
-
-
-
Max
-
-
0
0.8
−40 °C
to +125
°C
Min
V
CC
2.0
-
-
Max
-
-
0
0.8
V
V
V
V
Unit
C
I
-
4.0
-
-
-
pF
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
°C.
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
5 of 16
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