74LVC00A
Quad 2-input NAND gate
Rev. 7 — 25 April 2012
Product data sheet
1. General description
The 74LVC00A provides four 2-input NAND gates.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC00AD
74LVC00ADB
74LVC00APW
74LVC00ABQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74LVC00A
Quad 2-input NAND gate
4. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
terminal 1
index area
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
001aac939
00
11 4Y
10 3B
9
8
3A
3Y
GND
(1)
001aac938
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8,11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
74LVC00A
All information provided in this document is subject to legal disclaimers.
1
1A
00
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 25 April 2012
2 of 14
NXP Semiconductors
74LVC00A
Quad 2-input NAND gate
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[2]
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
±50
100
-
500
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
°C
V
O
> V
CC
or V
O
< 0 V
output in HIGH or LOW-state
V
O
= 0 V to V
CC
−0.5
-
-
−100
T
amb
=
−40 °C
to +125
°C
[3]
-
−65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
output HIGH or LOW state
Conditions
Min
1.65
1.2
0
0
−40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC00A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 25 April 2012
3 of 14
NXP Semiconductors
74LVC00A
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
−100 μA;
V
CC
= 1.65 V to 3.6 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−18
mA; V
CC
= 3.0 V
I
O
=
−24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
μA;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
CC
ΔI
CC
-
-
-
-
-
-
-
-
-
-
±0.1
0.1
5
0.2
0.45
0.6
0.4
0.55
±5
10
500
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
±20
40
5000
V
V
V
V
V
μA
μA
μA
V
CC
−
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
−
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
1.7
2.0
-
-
-
-
−40 °C
to +85
°C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
−40 °C
to +125
°C
Min
1.08
1.7
2.0
-
-
-
-
-
-
0.12
0.7
0.8
0.65
×
V
CC
-
Max
V
V
V
V
V
V
V
Unit
0.65
×
V
CC
-
0.35
×
V
CC
-
0.35
×
V
CC
V
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND -
current
supply
current
additional
supply
current
input
capacitance
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
−
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
-
-
C
I
-
4.0
-
-
-
pF
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
°C.
74LVC00A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 25 April 2012
4 of 14
NXP Semiconductors
74LVC00A
Quad 2-input NAND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 7.
Symbol Parameter
t
pd
propagation delay
Conditions
nA, nB to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
t
sk(o)
C
PD
output skew time
power dissipation
capacitance
V
CC
= 3.0 V to 3.6 V
per gate; V
I
= GND to V
CC
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
[1]
[2]
[3]
[4]
[3]
[4]
[2]
−40 °C
to +85
°C
Min
-
0.3
1.0
1.0
0.5
-
-
-
-
Typ
[1]
12
3.8
2.2
2.3
2.0
-
5.6
8.9
11.8
Max
-
8.4
4.8
5.1
4.3
1.0
-
-
-
−40 °C
to +125
°C
Unit
Min
-
0.3
1.0
1.0
0.5
-
-
-
-
Max
-
9.7
5.7
5.9
5.1
1.5
-
-
-
ns
ns
ns
ns
ns
ns
pF
pF
pF
Typical values are measured at T
amb
= 25
°C
and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
t
pd
is the same as t
PLH
and t
PHL
.
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs
11. Waveforms
V
I
nA, nB input
GND
t
PHL
V
OH
nY output
V
OL
V
M
mna213
V
M
t
PLH
V
M
= 1.5 V at V
CC
≥
2.7 V.
V
M
= 0.5
×
V
CC
at V
CC
< 2.7 V.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6.
The input (nA, nB) to output (nY) propagation delays
74LVC00A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 25 April 2012
5 of 14
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