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74HC1G00-Q100;
74HCT1G00-Q100
2-input NAND gate
Rev. 1 — 16 September 2013
Product data sheet
1. General description
The 74HC1G00-Q100; 74HCT1G00-Q100 is a single 2-input NAND gate. Inputs include
clamp diodes that enable the use of current limiting resistors to interface inputs to voltages
in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC1G00-Q100: CMOS level
For 74HCT1G00-Q100: TTL level
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC1G00GW-Q100
74HCT1G00GW-Q100
74HC1G00GV-Q100
74HCT1G00GV-Q100
40 C
to +125
C
40 C
to +125
C
Name
Description
Version
SOT353-1
SOT753
TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SC-74A
plastic surface-mounted package; 5 leads
Type number
NXP Semiconductors
74HC1G00-Q100; 74HCT1G00-Q100
2-input NAND gate
4. Marking
Table 2.
Marking codes
Marking
[1]
HA
TA
H00
T00
Type number
74HC1G00GW-Q100
74HCT1G00GW-Q100
74HC1G00GV-Q100
74HCT1G00GV-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
B
A
1
Y
4
2
mna097
mna098
&
4
A
Y
mna099
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
V
CC
Pin description
Pin
1
2
3
4
5
Description
data input
data input
ground (0 V)
data output
supply voltage
74HC_HCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
2 of 12
NXP Semiconductors
74HC1G00-Q100; 74HCT1G00-Q100
2-input NAND gate
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
25
65
Max
+7.0
20
20
12.5
25
-
+150
200
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 55
C,
the value of P
tot
derates linearly with 2.5 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC1G00-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
-
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT1G00-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
-
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
3 of 12
NXP Semiconductors
74HC1G00-Q100; 74HCT1G00-Q100
2-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at T
amb
= 25
C.
Symbol
Parameter
Conditions
40 C
to +85
C
Min
For type 74HC1G00-Q100
V
IH
HIGH-level input
voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level input
voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
2.0
mA; V
CC
= 4.5 V
I
O
=
2.6
mA; V
CC
= 6.0 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 2.0 mA; V
CC
= 4.5 V
I
O
= 2.6 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
V
IH
V
IL
V
OH
input leakage current
supply current
input capacitance
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
2.0
mA; V
CC
= 4.5 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 2.0 mA; V
CC
= 4.5 V
I
I
input leakage current
V
I
= V
CC
or GND; V
CC
= 5.5 V
-
-
-
0
0.15
-
0.1
0.33
1.0
-
-
-
0.1
0.4
1.0
V
V
A
4.4
4.13
4.5
4.32
-
-
4.4
3.7
-
-
V
V
2.0
-
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
- 1.5
1.6
1.2
0.1
0.1
0.1
0.33
0.33
1.0
10
-
-
0.8
-
-
-
-
-
-
-
-
2.0
-
0.1
0.1
0.1
0.4
0.4
1.0
20
-
-
0.8
V
V
V
V
V
A
A
pF
V
V
1.9
4.4
5.9
4.13
5.63
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Typ
Max
40 C
to +125
C
Min
Max
Unit
For type 74HCT1G00-Q100
74HC_HCT1G00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 September 2013
4 of 12
FPGA/CPLD
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