74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Rev. 1 — 21 February 2013
Product data sheet
1. General description
The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC10-Q100: CMOS level
For 74HCT10-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC10D-Q100
74HCT10D-Q100
74HC10PW-Q100
74HCT10PW-Q100
40 C
to +125
C
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
4. Functional diagram
1
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
mna757
2
1Y
12
13
3
2Y
6
4
5
&
12
&
6
A
3Y
8
9
10
11
mna759
&
8
B
C
Y
mna758
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
+&4
+&74
$
%
$
%
&
<
*1'
DDD
9
&&
&
<
&
%
$
<
+&4
+&74
$
%
$
%
&
<
*1'
DDD
9
&&
&
<
&
%
$
<
Fig 4.
Pin configuration SO14
Fig 5.
Pin configuration TSSOP14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
1C, 2C, 3C
1Y, 2Y, 3Y
V
CC
Pin description
Pin
1, 3, 9
2, 4, 10
7
13, 5, 11
12, 6, 8
14
Description
data input
data input
ground (0 V)
data input
data output
supply voltage
74HC_HCT10_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
2 of 13
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
6. Functional description
Table 3.
Input
nA
L
X
X
H
[1]
Function selection
[1]
Output
nB
X
L
X
H
nC
X
X
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO14 and TSSOP14 packages
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 package P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC_HCT10_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
3 of 13
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC10-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT10-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC10-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
2.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT10_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
4 of 13
NXP Semiconductors
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Table 6.
Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
C
I
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
=
20 A
I
O
=
4.0
mA
V
OL
I
I
I
CC
I
CC
LOW-level
output voltage
input leakage
current
supply current
additional
supply current
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 4.5 V
V
I
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input pin;
V
I
= V
CC
2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
-
-
-
-
0
-
-
150
0.1
0.1
2.0
540
-
-
-
-
0.1
1
20
675
-
-
-
-
0.1
1
40
735
V
A
A
A
4.4
3.98
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
Conditions
Min
-
25
C
Typ
3.5
Max
-
40 C
to +85
C 40 C
to +125
C
Unit
Min
-
Max
-
Min
-
Max
-
pF
74HCT10-Q100
V
IH
V
IL
V
OH
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
C
I
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see
Figure 7.
Symbol Parameter
Conditions
Min
74HC10-Q100
t
pd
propagation delay nA, nB to nY; see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation
capacitance
per package; V
I
= GND to V
CC
[3]
[2]
[1]
25
C
Typ
Max
40 C
to +125
C
Unit
Max
(85
C)
Max
(125
C)
-
-
-
-
-
-
-
-
30
11
9
9
19
7
6
12
95
19
-
16
75
15
13
-
120
24
-
20
95
19
16
-
145
29
-
25
110
22
19
-
ns
ns
ns
ns
ns
ns
ns
pF
74HC_HCT10_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2013
5 of 13
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