74AUP1G38
Low-power 2-input NAND gate (open drain)
Rev. 7 — 4 April 2016
Product data sheet
1. General description
The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The
output of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1G38
Low-power 2-input NAND gate (open drain)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G38GW
74AUP1G38GM
74AUP1G38GF
74AUP1G38GN
74AUP1G38GS
74AUP1G38GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP5
XSON6
XSON6
XSON6
XSON6
X2SON5
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
Version
SOT353-1
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8
0.8
0.35 mm
SOT1115
SOT1202
SOT1226
4. Marking
Table 2.
Marking
Marking code
[1]
aB
aB
aB
aB
aB
aB
Type number
74AUP1G38GW
74AUP1G38GM
74AUP1G38GF
74AUP1G38GN
74AUP1G38GS
74AUP1G38GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74AUP1G38
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 4 April 2016
2 of 19
NXP Semiconductors
74AUP1G38
Low-power 2-input NAND gate (open drain)
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration SOT353-1 (TSSOP5)
Fig 5.
Pin configuration SOT886 (XSON6)
Fig 6.
Pin configuration SOT891, SOT1115 and
SOT1202 (XSON6)
Fig 7.
Pin configuration SOT1226 (X2SON5)
6.2 Pin description
Table 3.
Symbol
A
B
GND
Y
n.c.
V
CC
Pin description
Pin
TSSOP5 and X2SON5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
data input
data input
ground (0 V)
data output
not connected
supply voltage
Description
74AUP1G38
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 4 April 2016
3 of 19
NXP Semiconductors
74AUP1G38
Low-power 2-input NAND gate (open drain)
7. Functional description
Table 4.
Input
A
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
Function table
[1]
Output
B
L
H
L
H
Y
Z
Z
Z
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
+20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP5 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode and Power-down mode
Conditions
Min
0.8
0
0
40
0
Max
3.6
3.6
3.6
+125
200
Unit
V
V
V
C
ns/V
74AUP1G38
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 4 April 2016
4 of 19
NXP Semiconductors
74AUP1G38
Low-power 2-input NAND gate (open drain)
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OZ
input leakage current
OFF-state output current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
= V
IH
or V
IL
(and at least one input
LOW); V
O
= 0 V to 3.6 V; V
CC
= 0 V to
3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
V
I
= V
CC
0.6 V; I
O
= 0 A; V
CC
= 3.3 V
V
CC
= 0 V to 3.6 V; V
I
= GND or V
CC
output enabled; V
O
= GND; V
CC
= 0 V
output disabled; V
O
= GND; V
CC
= 0 V
T
amb
=
40 C
to +85
C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
0.70
V
CC
0.65
V
CC
1.6
2.0
-
-
-
-
-
-
-
-
V
V
V
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.31
0.31
0.31
0.44
0.31
0.44
0.1
0.1
V
V
V
V
V
V
V
A
A
0.3
V
CC
V
0.70
V
CC
0.65
V
CC
1.6
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
Conditions
Min
Typ
Max
Unit
0.30
V
CC
V
0.35
V
CC
V
0.7
0.9
V
V
I
OFF
I
OFF
I
CC
I
CC
C
I
C
O
power-off leakage current
additional power-off
leakage current
supply current
additional supply current
input capacitance
output capacitance
-
-
-
-
-
-
-
-
-
-
-
0.8
1.7
1.1
0.2
0.2
0.5
40
-
-
-
A
A
A
A
pF
pF
pF
74AUP1G38
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 4 April 2016
5 of 19
MEMS传感器
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