Low Skew, ÷1/÷2,
3.3V LVPECL/ECL Clock Generator
G
ENERAL
D
ESCRIPTION
The 87322BI is a low skew, ÷1/÷2 3.3V LVPECL/ECL Clock
Generator. Using multiplexed/redundant clock inputs the
87322BI is designed to translate most differential signal levels
to LVPECL/ECL levels.
The CLK_SEL input selects between CLK0, nCLK0 and CLK1,
nCLK1 as the active input. The divide select inputs, DIV_SELA,
DIV_SELB, DIV_SELC, DIV_SELD, control the output frequen-
cy of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input can
be used to reset the internal dividers and disable the clock
outputs. Disabled outputs QAx, QBx, QCx and QDx will be
forced low. Disabled outputs nQAx, nQBx, nQCx and nQDx
will be forced high.
The 87322BI is characterized across the industrial
temperature range and over the supply voltage range of
3V to 3.8V for LVPECL and -3.8V to -3V for LVECL/ECL.
Guaranteed output and par t to par t skew character-
istics make the 87322BI an excellent choice for clock
generator and clock distribution applications demanding well
defined performance and repeatability.
87322BI
DATA SHEET
F
EATURES
•
Fifteen differential LVPECL outputs
•
Selectable LVPECL differential clock inputs
•
CLK0, nCLK0 and CLK1, nCLK1 can accept the
following differential input levels: LVPECL, LVDS, CML,
SSTL
•
Output frequency: 750MHz (maximum)
•
Output skew: 180ps (maximum)
•
Bank skew: 65ps (maximum)
•
Part-to-part skew: 500ps (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -3V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87322BI REVISION C 11/16/15
1
©2015 Integrated Device Technology, Inc.
87322BI DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
V
CC
MR
Power
Input
Type
Description
Core supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3C. LVCMOS /
Pulldown
LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3C. LVCMOS /
Pulldown
LVTTL interface levels.
Pulldown Non-inverting differential LVPECL clock input. LVPECL interface levels.
Pullup
Pulldown
Inverting differential LVPECL clock input. LVPECL interface levels.
Clock select. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects
CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Inverting differential LVPECL clock input. LVPECL interface levels.
No connect.
Selects divide value for Bank C output as described in Table 3C. LVCMOS /
LVTTL interface levels.
Selects divide value for Bank D output as described in Table 3C. LVCMOS /
Pulldown
LVTTL interface levels.
Pulldown
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3
4
5
6
7
8
9
10, 28, 29
11
12
13
14, 27, 30, 39,
40, 47, 52
15,16
17, 18
19, 20
21, 22
23, 24
25, 26
31, 32
33, 34
35, 36
37, 38
41, 42
43, 44
45, 46
48, 49
50, 51
DIV_SELA
DIV_SELB
CLK0
nCLK0
CLK_SEL
CLK1
nCLK1
nc
DIV_SELC
DIV_SELD
V
EE
V
CCO
nQD5, QD5
nQD4, QD4
nQD3, QD3
nQD2, QD2
nQD1, QD1
nQD0, QD0
nQC3, QC3
nQC2, QC2
nQC1, QC1
nQC0, QC0
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
Input
Input
Input
Input
Input
Input
Input
Unused
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown Non-inverting differential LVPECL clock input. LVPECL interface levels.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
LOW SKEW, ÷1/÷2,
3.3V LVPECL/ECL CLOCK GENERATOR
2
REVISION C 11/16/15
87322BI DATA SHEET
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
CLKx, nCLKx
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
CLK_SEL,
DIV_SELx, MR
Test Conditions
Minimum
Typical
2
4
51
51
Maximum
Units
pF
pF
kΩ
kΩ
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
MR CLK_SEL QA0:QA1
1
0
0
X
0
1
LOW
Active
Active
nQA0:nQA1
HIGH
Active
Active
QB0:QB2
LOW
Active
Active
HIGH
Active
Active
Outputs
nQB0:nQB2
QC0:QC3
LOW
Active
Active
nQC0:nQC3
HIGH
Active
Active
QD0:QD5
LOW
Active
Active
nQD0:nQD5
HIGH
Active
Active
T
ABLE
3B. I
NPUT
C
ONTROL
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
1
Clock Input
CLK0, nCLK0
CLK1, nCLK1
T
ABLE
3C. S
ELECT
P
IN
F
UNCTION
T
ABLE
Inputs
SEL_A SEL_B
0
1
0
1
SEL_C
0
1
SEL_D
0
1
QAx
÷1
÷2
Outputs
QBx
÷1
÷2
QCx
÷1
÷2
QDx
÷1
÷2
CLK
MR
Q ÷1
nQ ÷1
Q ÷2
nQ ÷2
F
IGURE
1. T
IMING
D
IAGRAM
REVISION C 11/16/15
3
LOW SKEW, ÷1/÷2,
3.3V LVPECL/ECL CLOCK GENERATOR
87322BI DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
42.3°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCO
I
EE
I
CCO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.8
3.8
160
98
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
MR, CLK_SEL,
F_SELA:F_SELD
MR, CLK_SEL,
F_SELA:F_SELD
MR, CLK_SEL,
F_SELA:F_SELD
MR, CLK_SEL,
F_SELA:F_SELD
V
CC
= V
IN
= 3.8V
V
IN
= 0V, V
CC
= 3.8V
-5
Test Conditions
Minimum
2
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
Input Low Current
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
CC
= V
IN
=3.8V
V
CC
= V
IN
=3.8V
V
IN
= 0V, V
CC
= 3.8V
V
IN
= 0V, V
CC
= 3.8V
-5
-150
0.15
V
EE
+ 1.5
V
CCO
- 1.4
V
CCO
- 2.0
0.6
1.0
V
CC
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage, NOTE 3
Output Low Voltage, NOTE 3
Peak-to-Peak Output Voltage Swing
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, CLK1 is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50W to V
CCO
- 2V.
LOW SKEW, ÷1/÷2,
3.3V LVPECL/ECL CLOCK GENERATOR
4
REVISION C 11/16/15
87322BI DATA SHEET
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(b)
tsk(pp)
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
20% to 80%
150
ƒ = 212MHz
1.5
Test Conditions
Minimum
Typical
Maximum
750
2.7
180
150
65
500
600
Units
MHz
ns
ps
ps
ps
ps
ps
All parameters measured at ƒ
≤
750MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
CCO
/2.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
CCO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
REVISION C 11/16/15
5
LOW SKEW, ÷1/÷2,
3.3V LVPECL/ECL CLOCK GENERATOR
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