Numonyx™ Wireless Flash Memory
(W18/W30 SCSP)
32WQ and 64WQ Family with Asynchronous RAM
Datasheet
Product Features
Device Architecture
— Flash Density: 32-Mbit, 64-Mbit
— Async PSRAM Density: 16-Mbit, 32-Mbit
— Top, Bottom or Dual flash parameter
configuration
Device Voltage
— Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V
— RAM VCC = 1.8 V or 3.0 V
Device Packaging
— 88 balls (8 x 10 active ball matrix)
— Area: 8x10 mm
— Height: 1.2 mm to 1.4 mm
PSRAM Performance
— 70 ns initial access, 25 ns async page reads at
1.8 V I/O
— 70 ns initial access async PSRAM at 1.8 V
I/O
— 70 ns initial access, 25 ns async page
reads at 3.0 V I/O
SRAM Performance
— 70 ns initial access at 1.8 V or 3.0 V I/O
Quality and Reliability
— Extended Temperature: –25 °C to +85 °C
— Minimum 100K flash block erase cycle
— 90 nm ETOX™ IX flash technology
— 130 nm ETOX™ VIII flash technology
Flash Performance
— 65 ns initial access at 1.8 V I/O
— 70 ns initial access at 3.0 V I/O
— 25 ns async page at 1.8 V or 3.0 V I/O
— 14 ns sync reads (t
CHQV
) at 1.8 V I/O
— 20 ns sync reads (t
CHQV
) at 3.0 V I/O
— Enhanced Factory Programming:
3.10 µs/Word (Typ)
Flash Architecture
— Read-While-Write/Erase
— Asymmetrical blocking structure
— 4-KWord parameter blocks (Top or
Bottom)
— 32-KWord main blocks
— 4-Mbit partition size
— 128-bit One-Time Programmable
(OTP) Protection Register
— Zero-latency block locking
— Absolute write protection with block
lock using F-VPP and F-WP#
Flash Software
— Numonyx™ Flash Data Integrator
(FDI) and Common Flash Interface
(CFI)
Order Number: 251407-13
November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
LL egal Lines and Disclaim ers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet
2
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Contents
1.0
Introduction
.............................................................................................................. 6
1.1
Nomenclature ..................................................................................................... 6
1.2
Conventions ....................................................................................................... 7
Functional Overview
.................................................................................................. 8
2.1
Block Diagram .................................................................................................... 8
2.2
Flash Memory Map and Partitioning........................................................................ 9
Package Information
............................................................................................... 10
Ballout and Signal Description
................................................................................. 13
4.1
Signal Ballout ................................................................................................... 13
4.2
Signal Descriptions ............................................................................................ 14
Maximum Ratings and Operating Conditions............................................................
16
5.1
Absolute Maximum Ratings................................................................................. 16
5.2
Operating Conditions ......................................................................................... 16
5.3
Capacitance...................................................................................................... 17
Electrical Specifications
........................................................................................... 18
6.1
DC Characteristics ............................................................................................. 18
AC Characteristics
................................................................................................... 20
7.1
Flash AC Characteristics ..................................................................................... 20
7.2
SRAM AC Characteristics .................................................................................... 20
7.3
PSRAM AC Characteristics................................................................................... 22
7.4
Device AC Test Conditions .................................................................................. 27
Flash Power Consumption
....................................................................................... 28
Device Operation
..................................................................................................... 29
9.1
Bus Operations ................................................................................................. 29
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 Flash Command Definitions
..................................................................................... 33
11.0 Flash Read Operations.............................................................................................
33
12.0 Flash Program Operations
....................................................................................... 33
13.0 Flash Erase Operations
............................................................................................ 33
14.0 Flash Security Modes
............................................................................................... 33
15.0 Flash Read Configuration Register
........................................................................... 33
16.0 SRAM Operations.....................................................................................................
34
16.1 Power-up Sequence and Initialization ................................................................... 34
16.2 Data Retention Mode ......................................................................................... 34
17.0 PSRAM Operations...................................................................................................
36
17.1 Power-Up Sequence and Initialization................................................................... 36
17.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).................................. 36
17.2 Standby Mode/ Deep Power-Down Mode............................................................... 37
17.3 PSRAM Special Read and Write Constraints ........................................................... 37
A
B
C
D
Write State Machine
................................................................................................ 38
Common Flash Interface..........................................................................................
38
Flash Flowcharts
..................................................................................................... 38
Additional Information
............................................................................................ 38
November 2007
Order Number: 251407-13
Datasheet
3
32WQ and 64WQ Family with Asynchronous RAM
E
F
Ordering Information (Active Line Items)
................................................................39
Ordering Information (Retired Line Items)
..............................................................40
Datasheet
4
November 2007
Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Revision History
Date
June 2003
September
2003
May 2004
August 2004
Revision
-001
-002
-006
-007
Initial release
Description
Changed PSRAM Read values.
Added new Transient Equivalent Testing Load Circuit figure.
General text edits.
Reformatted the datasheet and moved sections around according to the new layout.
Added 90 nm product information.
Added line items.
Added DC and AC specs for the new line items and edits to related sections.
Added line items.
Added 32WQ product information.
Added line items.
Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification
Updated Ordering Information
Updated Ordering information with active and retired line items.
Updated AC spec & power-up specs for 38F2030W0YxQE & 38F2040W0YxQE
Rempved 38F2030W0YxQE & 38F2040W0YxQE Line Items
Updated ordering information
Applied Numonyx branding.
January 2005
June 2005
October 2005
June 2007
August 2007
November 2007
-008
-009
-010
-011
-012
13
November 2007
Order Number: 251407-13
Datasheet
5
FPGA/CPLD
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