74LVC2245A
Octal transceiver with direction pin, 30
series termination
resistors; 5 V tolerant input/output; 3-state
Rev. 5 — 4 November 2011
Product data sheet
1. General description
The 74LVC2245A is a octal transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions.
A send/receive (DIR) input controls direction, and an output enable (OE) input makes
easy cascading possible. Pin OE controls the outputs so that the buses are effectively
isolated.
It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
The device is designed with 30
series termination resistors in both HIGH and LOW
output stages to reduce line noise.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Integrated 30
termination resistors
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC2245A
Octal transceiver with direction pin, 30
series termination resistors
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC2245AD
74LVC2245ADB
74LVC2245APW
74LVC2245ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
4. Functional diagram
1
DIR
OE
19
2
A0
B0
18
3
A1
B1
17
19
1
G3
3EN1 (BA)
3EN2 (AB)
4
A2
B2
16
5
1
2
3
4
5
6
7
8
9
mna365
A3
B3
15
2
18
17
16
15
14
13
12
11
6
A4
B4
14
7
A5
B5
13
8
A6
B6
12
9
A7
B7
11
mna174
Fig 1.
IEC logic symbol
Fig 2.
Logic symbol
74LVC2245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 4 November 2011
2 of 16
NXP Semiconductors
74LVC2245A
Octal transceiver with direction pin, 30
series termination resistors
5. Pinning information
5.1 Pinning
74LVC2245A
terminal 1
index area
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
GND
(1)
GND 10
B7 11
13 B5
12 B6
DIR
2
3
4
5
6
7
8
9
1
74LVC2245A
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
001aad041
A0
A1
A2
A3
A4
A5
A6
A7
GND 10
001aad042
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration SO20 and (T)SSOP20
Fig 4.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
DIR
A[0:7]
GND
B[0:7]
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
direction control input
data input/output
ground (0 V)
data input/output
output enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
OE
LOW
LOW
HIGH
DIR
LOW
HIGH
don’t care
Functional table
Input/output
An
A=B
input
Z (high-impedance OFF-state)
Bn
input
B=A
Z (high-impedance OFF-state)
74LVC2245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 4 November 2011
3 of 16
NXP Semiconductors
74LVC2245A
Octal transceiver with direction pin, 30
series termination resistors
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
output HIGH or LOW state
output 3-state
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVC2245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 4 November 2011
4 of 16
NXP Semiconductors
74LVC2245A
Octal transceiver with direction pin, 30
series termination resistors
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
2
mA; V
CC
= 1.65 V
I
O
=
4
mA; V
CC
= 2.3 V
I
O
=
6
mA; V
CC
= 2.7 V
I
O
=
9
mA; V
CC
= 3.0 V
I
O
=
12
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 2 mA; V
CC
= 1.65 V
I
O
= 4 mA; V
CC
= 2.3 V
I
O
= 6 mA; V
CC
= 2.7 V
I
O
= 12 mA; V
CC
= 3.0 V
I
I
I
OZ
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND
current
OFF-state
output
current
power-off
leakage
current
supply
current
additional
supply
current
input
capacitance
V
I
= V
IH
or V
IL
; V
CC
= 3.6 V;
V
O
= 5.5 V or GND;
V
CC
= 0 V; V
I
or V
O
= 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.2
0.45
0.6
0.4
0.55
5
5
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
20
V
V
V
V
V
A
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
V
CC
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
40 C
to +85
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.35
V
CC
0.7
0.8
40 C
to +125
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
Unit
0.35
V
CC
V
I
OFF
-
0.1
10
-
20
A
I
CC
I
CC
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
-
-
0.1
5
10
500
-
-
40
5000
A
A
C
I
-
4.0
-
-
-
pF
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
74LVC2245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 4 November 2011
5 of 16
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
