DATASHEET
82C84A
CMOS Clock Generator Driver
The 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both
CMOS and NMOS microprocessors such as the 80C86,
80C88, 8086 and the 8088. The chip contains a crystal
controlled oscillator, a divide-by-three counter and complete
“Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external
frequency source from DC to 25MHz. Crystal controlled
operation to 25MHz is guaranteed with the use of a parallel,
fundamental mode crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over
temperature and voltage ranges.
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design with
respect to power and/or speed requirements.
FN2974
Rev.4.01
Jan 23, 2020
Features
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
CSYNC
PCLK
AEN1
82C84A
(PDIP, CERDIP)
TOP VIEW
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
CC
X1
X2
ASYNC
EFI
F/C
OSC
RES
RESET
RDY1
READY
RDY2
AEN2
NC
4
5
6
7
8
82C84A (PLCC, CLCC)
TOP VIEW
V
CC
X1
19
3
2
1
20
NO
LO
NG
9
ER
IL
VA
A
AB
LE
R
O
S
O
PP
18
U
17
16
15
14
D
TE
R
X2
ASYNC
EFI
F/C
NC
10
GND
11
RESET
12
RES
13
OSC
FN2974 Rev.4.01
Jan 23, 2020
CLK
Page 1 of 14
82C84A
Ordering Information
PART
NUMBER
CP82C84AZ (see Note)
(Not available, not supported)
CS82C84A
(Not available, not supported)
MD82C84A/B
8406801VA
MR82C84A/B
(Not available, not supported)
PART
MARKING
CP82C84AZ
CS82C84A
MD82C84A/B
8406801VA
MR82C84A/B
TEMP. RANGE
(°C)
0 to +70
0 to +70
-55 to +125
-55 to +125
-55 to +125
PACKAGE
18 Ld PDIP* (Pb-free)
20 Ld PLCC
18 Ld CERDIP
18 Ld CERDIP SMD#
20 Pad CLCC
PKG. DWG.
#
E18.3
N20.35
F18.3
F18.3
J20.A
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2974 Rev.4.01
Jan 23, 2020
Page 2 of 14
82C84A
Functional Diagram
RES
X1
X2
11
17
16
XTAL
OSCILLATOR
D
CK
Q
10
RESET
12
OSC
F/C
EF1
CSYNC
RDY1
AEN1
RDY2
AEN2
ASYNC
13
14
1
4
3
6
7
15
CK
D
Q
FF1
3
SYNC
2
SYNC
2
PCLK
8
CLK
CK
5
D
Q
FF2
READY
CONTROL PIN
F/C
RES
RDY1, RDY2
AEN1, AEN2
ASYNC
LOGICAL 1
External Clock
Normal
Bus Ready
Address Disabled
1 Stage Ready
Synchronization
LOGICAL 0
Crystal Drive
Reset
Bus Not Ready
Address Enable
2 Stage Ready
Synchronization
FN2974 Rev.4.01
Jan 23, 2020
Page 3 of 14
82C84A
Pin Description
SYMBOL
AEN1,
AEN2
NUMBER
3, 7
TYPE
I
DESCRIPTION
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are
useful in system configurations which permit the processor to access two Multi-Master System Busses.
In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device
located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of
the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When
ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is
cleared after the guaranteed hold time to the processor has been met.
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times
the desired processor clock frequency, (Note 1).
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the
processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the
EFI input, (Note 1).
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency
appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK
output.
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly
connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI
input frequency and a 1/3 duty cycle.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK
and has a 50% duty cycle.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to
that of the crystal.
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration.
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing
characteristics are determined by RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be
synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.
When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be
externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to
ground.
Ground
V
CC
: The +5V power supply pin. A 0.1F capacitor between V
CC
and GND is recommended for
decoupling.
RDY1,
RDY2
ASYNC
4, 6
I
15
I
READY
X1, X2
F/C
5
17, 16
13
O
IO
I
EFI
14
I
CLK
8
O
PCLK
OSC
RES
2
12
11
O
O
I
RESET
CSYNC
10
1
O
I
GND
V
CC
NOTE:
9
18
1. If the crystal inputs are not used X1 must be tied to V
CC
or GND and X2 should be left open.
FN2974 Rev.4.01
Jan 23, 2020
Page 4 of 14
82C84A
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The
output of the oscillator is buffered and brought out on OSC
so that other system timing signals can be derived from this
stable, crystal-controlled source.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
Frequency
Type of Operation
Unwanted Modes
Load Capacitance
TYPICAL CRYSTAL SPEC
2.4 - 25MHz, Fundamental, “AT” cut
Parallel
6dB (Minimum)
18 - 32pF
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a
peripheral clock signal whose output frequency is 1/2 that of
CLK. PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to
accommodate two system busses. Each input has a qualifier
(AEN1 and AEN2, respectively). The AEN signals validate
their respective RDY signals. If a Multi-Master system is not
being used the AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in
normally ready systems do not require synchronization but
must satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY
synchronization operation.
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to flip-
flop one of the rising edge of CLK (requiring a setup time
tR1VCH) and the synchronized to flip-flop two at the next
falling edge of CLK, after which time the READY output will go
active (HIGH). Negative-going asynchronous READY inputs
will be synchronized directly to flip-flop two at the falling edge
of CLK, after which the READY output will go inactive. This
mode of operation is intended for use by asynchronous
(normally not ready) devices in the system which cannot be
guaranteed by design to meet the required RDY setup timing,
TR1VCL, on each bus cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
Capacitors C1, C2 are chosen such that their combined
capacitance
C1 x C2
-
CT =
---------------------
(Including stray capacitance)
C1 + C2
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is
accomplished with two flip-flops. (See Figure 1). The counter
output is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the
3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
FN2974 Rev.4.01
Jan 23, 2020
Page 5 of 14
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