FemtoClock™ Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
General Description
The ICS840004I is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Fibre Channel
HiPerClockS™
reference clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from IDT. Using a 26.5625MHz or a
26.04166MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency select pins
(F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz. The ICS840004I uses IDT’s 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typical random
rms phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS840004I is packaged in a small 20-pin TSSOP package.
ICS840004I
DATA SHEET
Features
•
•
•
•
•
•
Four single-ended LVCMOS/LVTTL outputs
17
Ω
typical output impedance
Selectable crystal oscillator interface or single-ended input
Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
VCO range: 560MHz - 700MHz
RMS phase jitter at 212.5MHz (637kHz – 10MHz):
0.49ps (typical)
Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
•
•
Frequency Select Function Table
Inputs
Input Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
F_SEL1
0
0
1
1
0
F_SEL0
0
1
0
1
1
M Divider
Value
24
24
24
24
24
N Divider
Value
3
4
6
12
4
M/N Ratio
Value
8
6
4
2
6
Output Frequency Range
(MHz)
212.5
159.375
106.25
53.125 (default)
156.25
Block Diagram
OE
Pullup
F_SEL1:0
Pullup:Pullup
nPLL_SEL
Pulldown
nXTAL_SEL
Pulldown
26.5625MHz
Pin Assignment
2
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
XTAL_IN
OSC
XTAL_OUT
REF_CLK
Pulldown
0
F_SEL1:0
1
Phase
Detector
00
01
10
11
Q0
1
VCO
0
N
÷3
÷4
÷6
÷12
(default)
Q1
ICS840004I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
Q2
M = ÷24 (fixed)
Q3
MR
Pulldown
ICS840004BGI REVISION B JULY 6, 2009
1
©2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 20
2, 9
3
4
5
Name
F_SEL0,
F_SEL1
nc
nXTAL_SEL
REF_CLK
OE
Input
Unused
Input
Input
Input
Pulldown
Pulldown
Pullup
Type
Pullup
Description
Frequency select pins. LVCMOS/LVTTL interface levels.
No connect.
Selects between the crystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
PLL bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply ground.
Single-ended clock outputs. 17
Ω
typical output impedance.
LVCMOS/ LVTTL interface levels.
Output supply pin.
6
MR
Input
Pulldown
7
8
10
11,
12
13, 19
14, 15, 17, 18
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2, Q1, Q0
V
DDO
Input
Power
Power
Input
Power
Output
Power
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
Test Conditions
Minimum
Typical
4
8
51
51
17
21
Maximum
Units
pF
pF
k
Ω
k
Ω
Ω
Ω
ICS840004BGI REVISION B JULY 6, 2009
2
©2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
2.375
Power Supply Current
Analog Supply Current
Output Supply Current
2.5
2.625
100
12
10
V
mA
mA
mA
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
Units
V
V
V
Table 3B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
95
12
8
Units
V
V
V
mA
mA
mA
ICS840004BGI REVISION B JULY 6, 2009
3
©2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 3C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
OE, F_SEL[0:1]
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
OE, F_SEL[0:1]
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= 3.465V
V
DD
= 2.625V
Input
High Current
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 3.3V ± 5% or 2.5V ± 5%
-5
-150
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IL
I
IH
I
IL
Input
Low Current
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
26.5625
50
7
1
MHz
Maximum
Units
Ω
pF
mW
ICS840004BGI REVISION B JULY 6, 2009
4
©2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
out
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew: NOTE 1, 2
212.5MHz, Integration Range:
637kHz – 10MHz
159.375MHz, Integration Range:
637kHz – 10MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, Integration Range:
1.875MHz – 20MHz
106.25MHz, Integration Range:
637kHz – 10MHz
53.125MHz, Integration Range:
637kHz – 10MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
250
40
42
48
0.49
0.55
0.56
0.79
0.65
800
60
58
52
Minimum
186.67
140
93.33
46.67
Typical
212.5
159.375
106.25
53.125
Maximum
226.66
170
113.33
56.66
60
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ICS840004BGI REVISION B JULY 6, 2009
5
©2009 Integrated Device Technology, Inc.
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