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54ACT 74ACT573 Octal Latch with TRI-STATE Outputs
April 1993
54ACT 74ACT573
Octal Latch with TRI-STATE Outputs
General Description
The ’ACT573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output En-
able (OE) inputs
The ’ACT573 is functionally identical to the ’ACT373 but has
inputs and outputs on opposite sides
Features
Y
Y
Y
Y
Y
Y
Y
Y
I
CC
and I
OZ
reduced by 50%
Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to ’ACT373
TRI-STATE outputs for bus interfacing
Outputs source sink 24 mA
’ACT573 has TTL-compatible inputs
Standard Military Drawing (SMD)
’ACT573 5962-87664
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment
for DIP Flatpak and SOIC
TL F 9973–1
TL F 9973 – 2
TL F 9973 – 3
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
Pin Assignment
for LCC
TL F 9973 – 4
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACT
TM
is a trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9973
RRD-B30M75 Printed in U S A
Functional Description
The ’ACT573 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the D
n
inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are en-
abled When OE is HIGH the buffers are in the high imped-
ance mode but this does not interfere with entering new
data into the latches
Truth Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
n
H
L
O
0
Z
H
e
HIGH Voltage
L
e
LOW Voltage
Z
e
High Impedance
X
e
Immaterial
O
0
e
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
TL F 9973 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
0 5V to
a
7 0V
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
e b
0 5V
V
I
e
V
CC
a
0 5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
e b
0 5V
V
O
e
V
CC
a
0 5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
CDIP
PDIP
b
20 mA
a
20 mA
b
0 5V to V
CC
a
0 5V
b
20 mA
a
20 mA
b
0 5V to V
CC
a
0 5V
g
50 mA
g
50 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
74ACT
54ACT
Minimum Input Edge Rate (DV
Dt)
’ACT Devices
V
IN
from 0 8V to 2 0V
V
CC
4 5V 5 5V
4 5V to 5 5V
0V to V
CC
0V to V
CC
b
40 C to
a
85 C
b
55 C to
a
125 C
125 mV ns
b
65 C to
a
150 C
175 C
140 C
Note 1
Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of FACT
TM
circuits outside databook specifications
DC Characteristics for ’ACT Family Devices
74ACT
Symbol
Parameter
V
CC
(V)
T
A
e a
25 C
Typ
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
45
55
45
55
45
55
45
55
V
OL
Maximum Low Level
Output Voltage
45
55
45
55
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum TRI-STATE
Leakage Current
55
55
0 001
0 001
15
15
15
15
4 49
5 49
20
20
08
08
44
54
3 86
4 86
01
01
0 36
0 36
g
0 1
54ACT
T
A
e
b
55 C to
a
125 C
74ACT
T
A
e
b
40 C to
a
85 C
Units
Conditions
Guaranteed Limits
20
20
08
08
44
54
3 70
4 70
01
01
0 50
0 50
g
1 0
20
20
08
08
44
54
3 76
4 76
01
01
0 44
0 44
g
1 0
V
V
V
V
OUT
e
0 1V
or V
CC
b
0 1V
V
OUT
e
0 1V
or V
CC
b
0 1V
I
OUT
e b
50
mA
V
IN
e
V
IL
or V
IH
b
24 mA
I
OH
b
24 mA
I
OUT
e
50
mA
V
IN
e
V
IL
or V
IH
24 mA
I
OL
24 mA
V
I
e
V
CC
GND
V
I
e
V
IL
V
IH
V
O
e
V
CC
GND
V
V
V
mA
mA
g
0 25
g
5 0
g
2 5
All outputs loaded thresholds on input associated with output under test
3
DC Characteristics for ’ACT Family Devices
(Continued)
74ACT
Symbol
Parameter
V
CC
(V)
T
A
e a
25 C
Typ
I
CCT
I
OLD
I
OHD
I
CC
Maximum
I
CC
Input
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
55
55
55
55
40
06
54ACT
T
A
e
b
55 C to
a
125 C
74ACT
T
A
e
b
40 C to
a
85 C
Units
Conditions
Guaranteed Limits
16
50
b
50
15
75
b
75
mA
mA
mA
mA
V
I
e
V
CC
b
2 1V
V
OLD
e
1 65V Max
V
OHD
e
3 85V Min
V
IN
e
V
CC
or GND
80 0
40 0
Maximum test duration 2 0 ms one output loaded at a time
Note
I
CC
for 54ACT
25 C is identical to 74ACT
25 C
AC Electrical Characteristics
74ACT
Symbol
Parameter
V
CC
(V)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
m
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
50
50
50
50
50
50
50
50
25
25
30
25
20
15
25
15
T
A
e a
25 C
C
L
e
50 pF
Typ
60
60
60
55
55
55
65
50
Max
10 5
10 5
10 5
95
10 0
95
11 0
85
54ACT
T
A
e b
55 C
to
a
125 C
C
L
e
50 pF
Min
15
15
15
15
15
15
15
15
Max
13 5
13 5
13 0
12 0
11 5
11 0
13 5
10 5
74ACT
T
A
e b
40 C
to
a
85 C
C
L
e
50 pF
Min
20
20
25
20
15
15
15
10
Max
12 0
12 0
12 0
10 5
11 0
10 5
12 5
95
ns
ns
ns
ns
ns
ns
ns
ns
Units
Voltage Range 5 0 is 5 0V
g
0 5V
4
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