74AHC123A; 74AHCT123A
Dual retriggerable monostable multivibrator with reset
Rev. 4 — 8 November 2011
Product data sheet
1. General description
The 74AHC123A; 74AHCT123A are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC123A; 74AHCT123A are dual retriggerable monostable multivibrators with
output pulse width control by three methods. The basic pulse time is programmed by
selection of an external resistor (R
EXT
) and capacitor (C
EXT
). The external resistor and
capacitor are normally connected as shown in
Figure 11.
Once triggered, the basic output pulse width may be extended by retriggering the gated
active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating
this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as
desired. Alternatively an output delay can be terminated at any time by a LOW-going edge
on input nRD, which also inhibits the triggering.
An internal connection from nRD to the input gate makes it possible to trigger the circuit by
a positive-going signal at input nRD as shown in
Table 3. Figure 8
and
Figure 9
illustrate
pulse control by retriggering and early reset. The basic output pulse width is essentially
determined by the value of the external timing components R
EXT
and C
EXT
. When
C
EXT
10 nF, the typical output pulse width is defined as: t
W
= R
EXT
C
EXT
where
t
W
= pulse width in ns; R
EXT
= external resistor in k; C
EXT
= external capacitor in pF.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2. Features and benefits
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
For 74AHC123A only: operates with CMOS input levels
For 74AHCT123A only: operates with TTL input levels
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74AHC123A; 74AHCT123A
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC123AD
74AHCT123AD
74AHC123APW
74AHCT123APW
74AHC123ABQ
74AHCT123ABQ
40 C
to +125
C
DHVQFN16
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
14
15
CX
RCX
&
13
1
14 1CEXT
6 2CEXT
15 1REXT/CEXT
7 2REXT/CEXT
S
Q
1A 1
2A 9
1B 2
2B 10
T
Q
RD
4 1Q
12 2Q
13 1Q
5 2Q
6
7
2
4
3
R
CX
RCX
&
5
9
10
1RD 3
2RD 11
001aae521
12
11
R
001aae522
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AHC_AHCT123A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 8 November 2011
2 of 22
NXP Semiconductors
74AHC123A; 74AHCT123A
Dual retriggerable monostable multivibrator with reset
nREXT/CEXT
V
CC
Q
RD
Q
V
CC
CL
R
CL
V
CC
R
R
CL
A
CL
CL
B
R
001aae524
For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND).
Fig 4. Functional diagram
74AHC_AHCT123A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 8 November 2011
4 of 22
NXP Semiconductors
74AHC123A; 74AHCT123A
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74AHC123A
74AHCT123A
terminal 1
index area
1B
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
9
001aah068
74AHC123A
74AHCT123A
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
2A
9
GND
(1)
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
1
1A
2A
001aah067
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO16, TSSOP16
Fig 6. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RD
2Q
1Q
1CEXT
1REXT/CEXT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
active HIGH output 2
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
active HIGH output 1
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74AHC_AHCT123A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 8 November 2011
5 of 22
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