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74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 7 — 8 February 2013
Product data sheet
1. General description
The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input
(DIR) and dual-supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at
any voltage between 0.8 V and 3.6 V making the device suitable for translating between
any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR
are referenced to V
CC(A)
and pins nB are referenced to V
CC(B)
. A HIGH on DIR allows
transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In Suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (<1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
NXP Semiconductors
74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AVC2T45DP
74AVC2T45DC
74AVC2T45GT
74AVC2T45GF
74AVC2T45GD
74AVC2T45GN
74AVC2T45GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP8
VSSOP8
XSON8
XSON8
XSON8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
SOT1089
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3
2
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT1116
SOT1203
4. Marking
Table 2.
Marking
Marking code
[1]
B45
B45
B45
B5
B45
B5
B5
Type number
74AVC2T45DP
74AVC2T45DC
74AVC2T45GT
74AVC2T45GF
74AVC2T45GD
74AVC2T45GN
74AVC2T45GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AVC2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 8 February 2013
2 of 27
NXP Semiconductors
74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
5. Functional diagram
DIR
5
DIR
1A
2
1A
7
1B
1B
2A
3
2A
6
V
CC(A)
V
CC(B)
V
CC(A)
001aag577
2B
2B
V
CC(B)
001aag578
Fig 1.
Logic symbol
Fig 2.
Logic diagram
6. Pinning information
6.1 Pinning
74AVC2T45
V
CC(A)
1A
2A
GND
1
2
3
4
001aag579
8
7
6
5
V
CC(B)
1B
2B
DIR
Fig 3.
Pin configuration SOT505-2 and SOT765-1
74AVC2T45
V
CC(A)
1
8
V
CC(B)
74AVC2T45
V
CC(A)
1A
1
2
3
4
8
7
6
5
V
CC(B)
1B
2B
DIR
1A
2
7
1B
2A
3
6
2B
2A
GND
4
5
DIR
GND
001aag580
001aai261
Transparent top view
Transparent top view
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
Fig 5.
Pin configuration SOT996-2
74AVC2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 8 February 2013
3 of 27
NXP Semiconductors
74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
6.2 Pin description
Table 3.
Symbol
V
CC(A)
1A
2A
GND
DIR
2B
1B
V
CC(B)
Pin description
Pin
1
2
3
4
5
6
7
8
Description
supply voltage A (referenced to pins 1A, 2A and DIR)
data input or output
data input or output
ground (0 V)
direction control
data input or output
data input or output
supply voltage B (referenced to pins 1B and 2B)
7. Functional description
Table 4.
Function table
[1]
Input
DIR
[3]
L
H
X
Input/output
[2]
nA
nA = nB
input
Z
nB
input
nB = nA
Z
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[4]
[1]
[2]
[3]
[4]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The input circuit of the data I/O is always active.
The DIR input circuit is referenced to V
CC(A)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into Suspend mode.
74AVC2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 8 February 2013
4 of 27
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