74AUP1T45
Low-power dual supply translating transceiver; 3-state
Rev. 5 — 9 August 2012
Product data sheet
1. General description
The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a
direction control input (DIR) and dual supply pins (V
CC(A)
and V
CC(B)
) which enable
bidirectional level translation. Both V
CC(A)
and V
CC(B)
can be supplied at any voltage
between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low
voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to
V
CC(A)
and pin B is referenced to V
CC(B)
. A HIGH on DIR allows transmission from A to B
and a LOW on DIR allows transmission from B to A.
Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall
times across the entire V
CC(A)
and V
CC(B)
ranges. The device ensures low static and
dynamic power consumption and is fully specified for partial power-down applications
using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow
current through the device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at GND, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 1.1 V to 3.6 V
V
CC(B)
: 1.1 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1T45GW
74AUP1T45GM
74AUP1T45GF
74AUP1T45GN
74AUP1T45GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
SOT1115
SOT1202
4. Marking
Table 2.
Marking
Marking code
[1]
p5
p5
p5
p5
p5
Type number
74AUP1T45GW
74AUP1T45GM
74AUP1T45GF
74AUP1T45GN
74AUP1T45GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
DIR
5
DIR
A
3
A
4
V
CC(A)
V
CC(B)
V
CC(A)
001aae962
B
B
V
CC(B)
001aae963
Fig 1.
Logic symbol
Fig 2.
Logic diagram
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 9 August 2012
2 of 36
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
6. Pinning information
6.1 Pinning
74AUP1T45
74AUP1T45
V
CC(A)
GND
1
2
6
5
V
CC(B)
DIR
A
A
3
001aae964
V
CC(A)
1
6
V
CC(B)
V
CC(A)
GND
74AUP1T45
1
2
3
6
5
4
V
CC(B)
DIR
B
GND
2
5
DIR
3
4
B
A
4
B
001aae965
001aae966
Transparent top view
Transparent top view
Fig 3.
Pin configuration SOT363
Fig 4.
Pin configuration SOT886
Fig 5.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
V
CC(A)
GND
A
B
DIR
V
CC(B)
Pin description
Pin
1
2
3
4
5
6
Description
supply voltage A
ground (0 V)
data input or output A
data input or output B
direction control DIR
supply voltage B
7. Functional description
Table 4.
Function table
[1]
Input
[2]
DIR
L
H
X
Input/output
[3]
A
A=B
input
suspend mode
B
input
B=A
suspend mode
Supply voltage
V
CC(A)
, V
CC(B)
1.1 V to 3.6 V
1.1 V to 3.6 V
GND
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
The DIR input circuit is referenced to V
CC(A)
.
The input circuit of the data I/Os are always active.
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 9 August 2012
3 of 36
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
V
O
< 0 V
Active mode
A port
B port
suspend or 3-state mode
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[1][2]
[1][2]
[1][2]
Conditions
Min
0.5
0.5
Max
+4.6
+4.6
-
+4.6
-
Unit
V
V
mA
V
mA
V
I
< 0 V
[1]
50
0.5
50
0.5
0.5
0.5
-
-
50
65
V
CC(A)
+ 0.5 V
V
CC(B)
+ 0.5 V
+4.6
20
50
-
+150
250
V
mA
mA
mA
C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
40 C
to +125
C
[3]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The values of V
CC(A)
and V
CC(B)
are provided in the recommended operating conditions; see
Table 6.
For SC-88 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC(A)
V
CC(B)
V
I
V
O
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage A
supply voltage B
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CCI
=1.1 V to 3.6 V
[1]
Conditions
Min
1.1
1.1
0
0
40
0
Max
3.6
3.6
3.6
V
CCO
+125
200
Unit
V
V
V
V
C
ns/V
V
CCO
is the supply voltage associated with the output port.
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 9 August 2012
4 of 36
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
C
V
IH
HIGH-level input
voltage
data input
V
CCI
= 1.1 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
CCI
= 3.0 V to 3.6 V
DIR input
V
CCI
= 1.1 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
CCI
= 3.0 V to 3.6 V
V
IL
LOW-level input
voltage
data input
V
CCI
= 1.1 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
CCI
= 3.0 V to 3.6 V
DIR input
V
CCI
= 1.1 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
CCI
= 3.0 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
I
O
=
20 A;
V
CC(A)
= V
CC(B)
= 1.1 V to 3.6 V
I
O
=
1.1
mA; V
CC(A)
= V
CC(B)
= 1.1 V
I
O
=
1.7
mA; V
CC(A)
= V
CC(B)
= 1.4 V
I
O
=
1.9
mA; V
CC(A)
= V
CC(B)
= 1.65 V
I
O
=
2.3
mA; V
CC(A)
= V
CC(B)
= 2.3 V
I
O
=
3.1
mA; V
CC(A)
= V
CC(B)
= 2.3 V
I
O
=
2.7
mA; V
CC(A)
= V
CC(B)
= 3.0 V
I
O
=
4.0
mA; V
CC(A)
= V
CC(B)
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IL
I
O
= 20
A;
V
CC(A)
= V
CC(B)
= 1.1 V to 3.6 V
I
O
= 1.1 mA; V
CC(A)
= V
CC(B)
= 1.1 V
I
O
= 1.7 mA; V
CC(A)
= V
CC(B)
= 1.4 V
I
O
= 1.9 mA; V
CC(A)
= V
CC(B)
= 1.65 V
I
O
= 2.3 mA; V
CC(A)
= V
CC(B)
= 2.3 V
I
O
= 3.1 mA; V
CC(A)
= V
CC(B)
= 2.3 V
I
O
= 2.7 mA; V
CC(A)
= V
CC(B)
= 3.0 V
I
O
= 4.0 mA; V
CC(A)
= V
CC(B)
= 3.0 V
I
I
input leakage
current
DIR input; V
I
= GND to V
CC(A)
;
V
CC(A)
= V
CC(B)
= 1.1 V to 3.6 V
[2]
[2]
[1][4]
[1][3]
[1][4]
[1][3]
Conditions
Min
Typ Max
Unit
0.65
V
CCI
1.6
2.0
-
-
-
-
-
-
-
-
-
0.35
V
CCI
0.7
0.9
V
V
V
V
V
V
V
V
V
0.65
V
CC(A)
-
1.6
2.0
-
-
-
-
-
-
V
CCO
0.1
0.75
V
CCO
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.35
V
CC(A)
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
V
CCO
0.31
0.31
0.31
0.44
0.31
0.44
0.1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
[2]
74AUP1T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 9 August 2012
5 of 36
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