74LVC573A
Rev. 7 — 30 March 2020
Octal D-type transparent latch
with 5 V tolerant inputs/outputs; 3-state
Product data sheet
1. General description
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an
Output Enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are
transparent, that is, a latch output changes each time its corresponding D-input changes. When
LE is LOW, the latches store the information that was present at the D-inputs one set-up time
preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH,
the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the
state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied
to the outputs. These features allow the use of these devices as translators in mixed 3.3 V or 5 V
applications.
The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin arrangement.
2. Features and benefits
•
•
•
•
•
•
•
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
•
JESD8-7A (1.65 V to 1.95 V)
•
JESD8-5A (2.3 V to 2.7 V)
•
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-B exceeds 200 V
•
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC573AD
74LVC573ADB
74LVC573APW
74LVC573ABQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
11
1
1
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
C1
EN1
19
18
17
16
15
14
13
12
mna808
2
3
4
5
6
7
8
9
1D
mna807
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 LE
1 OE
mna809
Fig. 3.
Functional diagram
74LVC573A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 30 March 2020
2 / 17
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig. 4.
Logic diagram
5. Pinning information
5.1. Pinning
74LVC573A
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
aaa-029010
74LVC573A
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
aaa-029011
GND 10
GND 10
Fig. 5.
Pin configuration SOT163-1 (SO20)
Fig. 6.
Pin configuration SOT339-1 (SSOP20) and
SOT360-1 (TSSOP20)
74LVC573A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 30 March 2020
3 / 17
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC573A
terminal 1
index area
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
GND 10
LE 11
GND
(1)
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
OE
1
aaa-029012
Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,
the solder land should remain floating or connected to GND.
Fig. 7.
Pin configuration SOT764-1 (DHVQFN20)
5.2. Pin description
Table 2. Pin description
Symbol
OE
LE
D0, D1, D2, D3, D4, D5, D6, D7
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
V
CC
Pin
1
11
2, 3, 4, 5, 6, 7, 8, 9
19, 18, 17, 16, 15, 14, 13, 12
10
20
Description
output enable input (active LOW)
latch enable input (active HIGH)
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3. Functional table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
Operating modes
Enable and read register
(transparent mode)
Latch and read register
Input
OE
L
L
L
L
Latch register and disable outputs H
H
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
L
H
L
H
L
H
Internal latch
Output
Qn
L
H
L
H
Z
Z
74LVC573A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 30 March 2020
4 / 17
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Conditions
V
I
< 0
[1]
V
O
> V
CC
or V
O
< 0
[2]
V
O
= 0 V to V
CC
Min
-0.5
-50
-0.5
-
-0.5
-
-
-100
-65
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SOT163-1 (SO20) package: P
tot
derates linearly with 12.3 mW/K above 109 °C.
For SOT339-1 (SSOP20) packages: P
tot
derates linearly with 10.0 mW/K above 100 °C.
For SOT360-1 (TSSOP20) package: P
tot
derates linearly with 10.0 mW/K above 100 °C.
For SOT764-1 (DHVQFN20) package: P
tot
derates linearly with 12.9 mW/K above 111 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
output HIGH- or LOW-state
output 3-state
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Min
1.65
1.2
0
0
0
-40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
74LVC573A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 30 March 2020
5 / 17
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