74LVC373A-Q100
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 1 — 17 April 2013
Product data sheet
1. General description
The 74LVC373A-Q100 consists of eight D-type transparent latches, featuring separate
D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch
enable input (pin LE) and an output enable input (pin OE) are common to all internal
latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output changes each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE. When pin OE is LOW, the contents of the eight latches are available at the
Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can
be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs. These features allow the use of these devices as translators in mixed 3.3 V
and 5 V applications. The 74LVC373A-Q100 is functionally identical to the
74LVC573A-Q100, but has a different pin arrangement.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LVC373A-Q100
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC373AD-Q100
74LVC373ADB-Q100
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
74LVC373APW-Q100
40 C
to +125
C
74LVC373ABQ-Q100
40 C
to +125
C
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
4. Functional diagram
1
18
17
14
13
8
7
4
3
D7
D6
D5
D4
D3
D2
D1
D0
LE
11
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE
18
mna881
EN
C1
19
16
15
12
9
11
3
4
7
8
1D
2
5
6
9
12
15
16
19
mna880
6
5
2
13
14
17
1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC373A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
2 of 19
NXP Semiconductors
74LVC373A-Q100
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
LE
Q4 12
Q5 15
Q6 16
Q7 19
LE
LE
11 LE
1 OE
mna882
D
LE
Q
mna189
Fig 3.
Functional diagram
Fig 4.
Logic diagram for one latch
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna883
Fig 5.
Logic diagram
74LVC373A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
3 of 19
NXP Semiconductors
74LVC373A-Q100
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
/9&$4
WHUPLQDO
LQGH[ DUHD
9
&&
4
'
'
4
4
'
*1'
*1'
/(
'
4
2(
/9&$4
2(
4
'
'
4
4
'
'
4
9
&&
4
'
'
4
4
'
'
4
/(
DDD
4
'
'
4
4
'
'
4
*1'
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6.
Pin configuration for SO20 and (T)SSOP20
Fig 7.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
LE
D[0:7]
Q[0:7]
GND
V
CC
Pin description
Pin
1
11
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
10
20
Description
output enable input (active LOW)
latch enable input (active HIGH)
data input
latch output
ground (0 V)
supply voltage
74LVC373A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
4 of 19
NXP Semiconductors
74LVC373A-Q100
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3.
Functional table
[1]
Input
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High-impedance OFF-state
Operating modes
Internal latch
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
L
L
L
L
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0
HIGH or LOW-state
3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC373A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
5 of 19
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