Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
FEATURES
•
Wide operating voltage: 1.0 to 5.5V
•
Optimized for Low Voltage applications: 1.0V to 3.6V
•
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
•
Typical V
OLP
(output ground bounce) < 0.8V at V
CC
= 3.3V,
•
Typical V
OHV
(output V
OH
undershoot) > 2V at V
CC
= 3.3V,
•
Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
n
inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
•
Useful as input or output port for microprocessors/microcomputer
•
Common 3-State output enable input
•
Output capability: bus driver
•
I
CC
category: MSI
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
Dn to Qn
LE to Qn
Input capacitance
Power dissipation capacitance per latch
Notes 1, 2
CONDITIONS
C
L
= 15pF
V
CC
= 3.3V
TYPICAL
12
13
3.5
26
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
x f
i
)
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH
AMERICA
74LV573 N
74LV573 D
74LV573 DB
74LV573 PW
NORTH AMERICA
74LV573 N
74LV573 D
74LV573 DB
74LV573PW DH
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10
11
20
SYMBOL
OE
D0–D7
Q0–Q7
GND
LE
VCC
FUNCTION
Output enabled input (active LOW)
Data inputs
Data outputs
Ground (0V)
Latch enable input (active HIGH)
Positive supply voltage
1998 Jun 10
2
853-1989 19545
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– bus driver outputs
DC V
CC
or GND current for types with
–bus driver outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
35
70
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
P
t t
tot
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
Input voltage
Output voltage
Operating ambient temperature range in free
air
Input rise and fall times
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
PARAMETER
DC supply voltage
CONDITIONS
See Note 1
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
–
–
TYP.
3.3
–
–
MAX
5.5
V
CC
V
CC
+85
+125
500
200
100
50
UNIT
V
V
V
°C
t
r
, t
f
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
1998 Jun 10
5
NXP MCU
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