The UT54ACTS245E is a non-inverting octal bus transceiver
designed for asynchronous two-way communication between
data buses. The control function implementation minimizes
external timing requirements.
The device allows data transmission from the A bus to the B
bus or from the B bus to the A bus depending upon the logic
level at the direction control (DIR) input. The enable input (G)
disables the device so that the buses are effectively isolated.
The device is characterized over full HiRel temperature range
of -55°C to +125°C.
FUNCTION TABLE
ENABLE
G
L
L
H
DIRECTION
CONTROL DIR
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
PINOUTS
20-Lead Flatpack
Top View
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
G
B1
B2
B3
B4
B5
B6
B7
B8
LOGIC SYMBOL
G
DIR
(19)
(1)
G3
3 EN1 (BA)
3 EN2 (AB)
(18)
1
2
(17)
(16)
(15)
(14)
B1
B2
B3
B4
A1
A2
A3
A4
A5
A6
A7
A8
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
B5
(13)
B6
(12)
B7
(11)
B8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
LOGIC DIAGRAM
DIR
(1)
(19)
G
A1
(2)
(18)
B1
A2
(3)
(17)
B2
A3
(4)
(16)
B3
A4
(5)
(15)
B4
A5
(6)
(14)
B5
A6
(7)
(13)
B6
A7
(8)
(12)
B7
A8
(9)
(11)
B8
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
108
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum package power dissipation
permitted @ Tc = +125
o
C
LIMIT
-0.3 to 6.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
15
±10
3.3
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS245E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL1
V
IL2
V
IH1
V
IH2
I
IN
V
OL1
DESCRIPTION
Low-level input voltage
1
Low-level input voltage
1
High-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
IN
= V
DD
or V
SS
I
OL
= 12mA
V
DD
= 4.5V to 5.5V
V
OL2
Low-level output voltage
3
I
OL
= 8mA
V
DD
= 3.0V to 3.6V
V
OH1
High-level output voltage
3
I
OH
= -12mA
V
DD
from 4.5V to 5.5V
V
OH2
High-level output voltage
3
I
OH
= -8mA
V
DD
from 3.0V to 3.6V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
-8
mA
-12
mA
8
mA
12
mA
-200
200
mA
-300
300
mA
2.4
V
0.7 V
DD
V
0.4
V
0.5 V
DD
2.0
-1
1
0.4
MIN
MAX
0.8
0.8
UNIT
V
V
V
V
μA
V
4
I
OZH
Three-state output leakage cur-
rent, high
G = 5.5V; for all other inputs
V
IN
= V
DD
or V
SS;
V
OUT =
V
DD
V
DD
= 5.5V
30
μA
I
OZL
Three-state output leakage cur-
rent, low
G = 5.5V; for all other inputs
V
IN
= V
DD
or V
SS;
V
OUT =
V
SS
V
DD
= 5.5V
-30
μA
P
total1
Power dissipation
2, 8
C
L
= 50pF
V
DD
= 4.5V to 5.5V
1.5
mW/
MH
Z
mW/
MH
Z
μA
P
total2
Power dissipation
2, 8
C
L
= 50pF
V
DD
= 3.0V to 3.6V
.75
I
DDQ
ΔI
DDQ
Quiescent Supply Current
V
IN
= V
DD
or V
SS
V
DD
from 3.0V to 5.5V
10
Quiescent Supply Current
Delta
For input under test
V
IN
= V
DD
-2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
ƒ
= 1MHz, V
DD
= 0V
ƒ
= 1MHz, V
DD
= 0V
1.6
mA
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
15
15
pF
pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power does not include power contribution of any TTL output sink current.
9. Guaranteed by characterization, but not tested.
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