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74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Rev. 1 — 10 August 2012
Product data sheet
1. General description
The 74HC373-Q100; 74HCT373-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A
latch enable (LE) input and an output enable (OE) input are common to all latches.
The 74HC373-Q100; 74HCT373-Q100 consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output changes state each time its
corresponding D input changes.
When LE is LOW, the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373-Q100; 74HCT373-Q100 is functionally identical to:
•
74HC573-Q100; 74HCT573-Q100: but different pin arrangement
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC373-Q100: CMOS level
For 74HCT373-Q100: TTL level
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Functionally identical to the 74HC573-Q100; 74HCT573-Q100
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC373D-Q100
74HCT373D-Q100
74HC373PW-Q100
74HCT373PW-Q100
74HC373BQ-Q100
74HCT373BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP20
40 C
to +125
C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
4. Functional diagram
3
4
7
8
13
14
17
18
11
1
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
LATCH
1 TO 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae050
Fig 1.
Functional diagram
OE
LE
11
3
4
7
8
13
14
17
18
LE
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
001aae048
1
11
EN
C1
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
001aae049
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
2 of 24
NXP Semiconductors
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
LE
LE
LE
D
Q
LE
001aae051
Fig 4.
Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5.
Logic diagram
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
3 of 24
NXP Semiconductors
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
+&4
+&74
2(
4
'
'
4
4
'
'
4
9
&&
4
'
'
4
4
'
'
4
/(
DDD
+&4
+&74
WHUPLQDO
LQGH[ DUHD
4
'
'
4
4
'
'
4
*1'
9
&&
4
'
'
4
4
'
'
4
*1'
2(
*1'
/(
DDD
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 6.
Pin configuration SO20 and TSSOP20
Fig 7.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
LE
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
3-state output enable input (active LOW)
3-state latch output
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
4 of 24
FPGA/CPLD
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