74HC259; 74HCT259
8-bit addressable latch
Rev. 7 — 2 September 2020
Product data sheet
1. General description
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of
operation. In the addressable latch mode, data on the D input is written into the latch addressed
by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches
will retain their previous states. In memory mode, all latches retain their previous states and are
unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs
are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
•
•
•
Wide supply voltage range from 2.0 V to 6.0 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Input levels:
•
For 74HC259: CMOS level
•
For 74HCT259: TTL level
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
•
CDM JESD22E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
•
•
Nexperia
74HC259; 74HCT259
8-bit addressable latch
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC259D
74HCT259D
74HC259PW
74HCT259PW
74HC259BQ
74HCT259BQ
-40 °C to +125 °C
DHVQFN16
-40 °C to +125 °C
TSSOP16
-40 °C to +125 °C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT403-1
SOT763-1
4. Functional diagram
13
15
14
Z9
G8
G10
9,10D
0
0
G
2
0
7
1
2
3
4
5
6
7
mna573
mna572
14
LE
13
Q0
D
Q1
Q2
1
2
3
Q3
A0
A1
A2
MR
15
Q4
Q5
Q6
Q7
1
DX
1
C10
8R
4
5
6
7
9
10
11
12
4
5
6
7
9
10
11
12
2
3
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Q0
1
2
3
A0
A1
A2
1-of-8
DECODER
8 LATCHES
14
15
13
LE
MR
D
Q1
Q2
Q3
Q4
4
5
6
7
9
Q5 10
Q6 11
Q7 12
mna571
Fig. 3.
Functional diagram
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 2 September 2020
2 / 17
Nexperia
74HC259; 74HCT259
8-bit addressable latch
5. Pinning information
5.1. Pinning
74HC259
74HCT259
terminal 1
index area
A1
2
3
4
5
6
7
8
GND
Q4
9
GND
(1)
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
A0
1
74HC259
74HCT259
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
001aaj444
A2
Q0
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9
Q4
Q1
Q2
Q3
001aaj445
Transparent top view
Fig. 4.
Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT763-1 (DHVQFN16)
5.2. Pin description
Table 2. Pin description
Symbol
A0, A1, A2
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
D
LE
MR
V
CC
Pin
1, 2, 3
4, 5, 6, 7, 9, 10, 11, 12
8
13
14
15
16
Description
address input
latch output
ground (0 V)
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 2 September 2020
3 / 17
Nexperia
74HC259; 74HCT259
8-bit addressable latch
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Reset (clear)
Input
MR
L
L
Demultiplexer
(active HIGH 8-channel) L
decoder (when D = H)
L
L
L
L
L
L
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Output
Q0
L
L
L
L
L
L
L
L
q
0
q
0
q
0
q
0
q
0
q
0
q
0
q
0
Q1
L
Q2
L
L
Q3
L
L
L
Q4
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
L
Q7
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
Q=d L
L
L
L
L
L
L
q
1
Q=d L
L
L
L
L
L
q
2
q
2
Q=d L
L
L
L
L
q
3
q
3
q
3
Q=d L
L
L
L
q
4
q
4
q
4
q
4
Q=d L
L
L
q
5
q
5
q
5
q
5
q
5
Q=d L
L
q
6
q
6
q
6
q
6
q
6
q
6
Q=d L
Q = d q
1
q
1
q
1
q
1
q
1
q
1
q
1
Q = d q
2
q
2
q
2
q
2
q
2
q
2
Q = d q
3
q
3
q
3
q
3
q
3
Q = d q
4
q
4
q
4
q
4
Q = d q
5
q
5
q
5
Q = d q
6
q
6
Q = d q
7
Table 4. Operating mode select table
H = HIGH voltage level; L = LOW voltage level.
LE
L
H
L
H
MR
H
H
L
L
Mode
Addressable latch mode
Memory mode
Demultiplexer mode
Reset mode
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 2 September 2020
4 / 17
Nexperia
74HC259; 74HCT259
8-bit addressable latch
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-70
-65
Max
+7.0
±20
±20
±25
+70
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT109-1 (SO16) package: P
tot
derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: P
tot
derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: P
tot
derates linearly with 11.2 mW/K above 106 °C.
8. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
74HC259
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
-40
-
-
-
74HCT259
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC259
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25 °C
Typ
Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
74HC_HCT259
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 2 September 2020
5 / 17
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