HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V I/O
Features:
x
x
PRELIMINARY
IDT70V3569S
x
x
x
x
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial: 4.2/5/6ns (max.)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
Fast 4.2ns clock to data out
1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
x
x
x
x
x
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-ball fine-pitch Ball Grid Array
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B
W
2
L
B B
WW
3 3
L R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
16K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
13L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
13R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4831 tbl 01
OCTOBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC 4831/6
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
The IDT70V3569 is a high-speed 16K x 36 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3569 has been optimized for applications having unidirectional or
Description:
bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3569 can support an I/O operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V
DD
) remains at 3.3V.
Pin Configuration
(1,2,3,4)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
IO
19L
IO
18L
B1
B2
V
SS
B3
NC
B4
NC
B5
NC
B6
A
12L
B7
A
8L
B8
BE
1L
B9
V
DD
B10
CLK
L
CNTEN
L
A
4L
B11
B12
B13
A
0L
B14
OPT
L
I/O
17L
V
SSQR
B15
B16
B17
I/O
20R
V
SSQR
I/O
18R
C1
C2
C3
V
SS
C4
NC
C5
A
13L
C6
A
9L
C7
BE
2L
C8
CE
0L
C9
V
SS
C10
ADS
L
C11
A
5L
C12
A
1L
C13
V
SS
C14
V
DDQR
I/O
16L
I/O
15R
C15
C16
C17
V
DDQL
I/O
19R
V
DDQR
V
DD
D1
D2
D3
D4
NC
D5
NC
D6
A
10L
D7
BE
3L
D8
CE
1L
D9
V
SS
D10
R/
W
L
D11
A
6L
D12
A
2L
D13
V
DD
I/O
16R
I/O
15L
V
SSQL
D14
D15
D16
D17
I/O
22L
V
SSQL
I/O
21L
I/O
20L
E1
E2
E3
E4
NC
A
11L
A
7L
BE
0L
V
DD
OE
L
CNTRST
L
A
3L
V
DD
I/O
17R
V
DDQL
I/O
14L
I/O
14R
E14
E15
E16
E17
I/O
23L
I/O
22R
V
DDQR
I/O
21R
F1
F2
F3
F4
I/O
12L
I/O
13R
V
SSQR
I/O
13L
F14
F15
F16
F17
V
DDQL
I/O
23R
I/O
24L
V
SSQR
G1
G2
G3
G4
V
SSQL
I/O
12R
I/O
11L
V
DDQR
G14
G15
G16
G17
I/O
26L
V
SSQL
I/O
25L
I/O
24R
H1
H2
H3
H4
I/O
9L
V
DDQL
I/O
10L
I/O
11R
V
DD
J1
I/O
26R
V
DDQR
I/O
25R
J2
J3
J4
70V3569BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
H14
H15
H16
H17
V
DD
J14
IO
9R
V
SSQR
I/O
10R
J15
J16
J17
V
DDQL
K1
V
DD
K2
V
SS
K3
V
SSQR
K4
V
SSQL
K14
V
DD
K15
V
SS
V
DDQR
K16
K17
I/O
28R
V
SSQL
I/O
27R
L1
L2
L3
V
SS
L4
I/O
7R
V
DDQL
I/O
8R
L14
L15
L16
V
SS
L17
I/O
29R
I/O
28L
V
DDQR
I/O
27L
M1
M2
M3
M4
I/O
6R
M14
I/O
7L
V
SSQR
I/O
8L
M15
M16
M17
V
DDQL
I/O
29L
I/O
30R
V
SSQR
N1
N2
N3
N4
V
SSQL
I/O
6L
I/O
5R
V
DDQR
N14
N15
N16
N17
I/O
31L
V
SSQL
I/O
31R
I/O
30L
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
I/O
3R
V
DDQL
I/O
4R
P14
P15
P16
I/O
5L
P17
I/O
32R
I/O
32L
V
DDQR
I/O
35R
R1
R2
R3
R4
NC
R5
NC
R6
A
12R
R7
A
8R
R8
BE
1R
R9
V
DD
R10
CLK
R
CNTEN
R
A
4R
R11
R12
R13
I/O
2L
R14
I/O
3L
V
SSQR
I/O
4L
R15
R16
R17
V
SSQR
I/O
33L
I/O
34R
T1
T2
T3
NC
T4
NC
T5
A
13R
T6
A
9R
T7
BE
2R
CE
0R
T8
T9
V
SS
T10
ADS
R
T11
A
5R
T12
A
1R
T13
V
SS
T14
V
DDQL
I/O
1R
V
DDQR
T15
T16
T17
I/O
33R
U1
I/O
34L
V
DDQL
V
SS
U2
U3
U4
NC
U5
NC
U6
A
10R
U7
BE
3R
U8
CE
1R
U9
V
SS
U10
R/
W
R
A
6R
U12
A
2R
U13
V
SS
U14
I/O
0R
V
SSQL
I/O
2R
U15
U16
U17
V
SSQL
I/O
35L
V
DD
NC
NC
A
11R
A
7R
BE
0R
V
DD
OE
R
A
3R
A
0R
V
DD
OPT
R
I/O
0L
I/O
1L
,
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
and V
SSQ
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4831 drw 02c
6.42
2
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
V
SSQR
V
DDQR
I/O
18R
I/O
18L
V
SS
V
DD
V
SS
NC
NC
NC
NC
NC
NC
NC
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
BE
3L
BE
2L
BE
1L
BE
0L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
CNTRST
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
V
DD
V
DD
V
SS
OPT
L
I/O
17L
I/O
17R
V
DDQR
V
SSQR
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SSQL
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SSQR
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SSQL
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SSQR
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SSQL
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SSQR
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SSQL
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SSQR
I/O
33R
I/O
33L
I/O
34R
I/O
34L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V3569DR
DR-208
(5)
208-Pin PQFP
Top View
(6)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SSQL
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SSQR
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SSQL
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SSQR
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SSQL
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SSQR
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SSQL
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SSQR
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
and V
SSQ
pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
V
SSQL
V
DDQL
I/O
35R
I/O
35L
V
DD
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
BE
3R
BE
2R
BE
1R
BE
0R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
CNTRST
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
DD
V
SS
V
SS
OPT
R
I/O
0L
I/O
0R
V
DDQL
V
SSQL
4831 drw 02a
6.42
3
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
13L
I/O
0L
- I/O
35L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
BE
0L
-
BE
3L
V
DDQL
V
SSQL
OPT
L
V
DD
V
SS
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
13R
I/O
0R
- I/O
35R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
BE
0R
-
BE
3R
V
DDQR
V
SSQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Byte Enables (9-bit bytes)
Power (I/O Bus)
(3.3V or 2.5V)
(1)
Names
Ground (I/O Bus)
(0V)
Option for selection V
DDQX
(1,2)
Power
Ground
(3.3V)
(1)
(0V)
4831 tbl 01
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on I/O
X
.
2. OPT
X
selects the operating voltage levels for the I/Os on that port. If OPT
X
is set to VIH (3.3V), then that port's I/Os will operate at 3.3V levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that port's I/Os will operate
at 2.5V levels and V
DDQX
must be supplied at 2.5V. The OPT pins are indepen-
dent of one anotherboth ports can operate at 3.3V levels, both can operate at
2.5V levels, or either can operate at 3.3V with the other at 2.5V.
Truth Table IRead/Write and Enable Control
(1,2,3,4)
OE
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
CE
0
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE
1
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
BE
3
X
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
L
BE
2
X
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
L
BE
1
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
L
BE
0
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
L
R/W
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
Byte 3
I/O
27-35
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
IN
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
OUT
High-Z
Byte 2
I/O
18-26
High-Z
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
D
IN
High-Z
High-Z
D
OUT
High-Z
High-Z
D
OUT
D
OUT
High-Z
Byte 1
I/O
9-17
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
D
IN
High-Z
D
IN
High-Z
D
OUT
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
Byte 0
I/O
0-8
High-Z
High-Z
High-Z
D
IN
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
High-Z
MODE
DeselectedPower Down
DeselectedPower Down
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
4831 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= V
IH
.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
6.42
4
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control
(1,2)
Address
X
An
An
X
Previous
Address
X
X
Ap
Ap
Addr
Used
0
An
Ap
Ap + 1
CLK
(6)
↑
↑
↑
↑
ADS
X
L
(4)
H
H
CNTEN
X
H
H
L
(5)
CNTRST
L
(4)
H
H
H
I/O
(3)
D
I/O
(0)
D
I/O
(n)
D
I/O
(p)
D
I/O
(p+1)
Counter Reset to Address 0
External Address Loaded into Counter
External Address BlockedCounter disabled (Ap reused)
Counter EnabledInternal Address generation
4831 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W,
CE
0
, CE
1
,
BEn
and
OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other memory control signals including
CE
0
, CE
1
and
BEn
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
BEn.
Recommended Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
150mV
3.3V
+
150mV
4831 tbl 04
Recommended DC Operating
Conditions with V
DDQ
at 2.5V
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
(3)
Ground
Input High Voltage
(Address & Control Inputs)
Input High Voltage - I/O
(3)
Input Low Voltage
Min.
3.15
2.375
0
2.0
1.7
-0.3
(1)
Typ.
3.3
2.5
0
____
Max.
3.45
2.625
0
V
DDQ
+ 125mV
(2)
V
DDQ
+ 125mV
(2)
0.7
Unit
V
V
V
V
V
V
4831 tbl 05a
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
____
____
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
NOTES:
1. V
IL >
-1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DDQ
+ 125mV.
3. To select operation at 2.5V levels on the I/Os of a given port, the OPT pin for
that port must be set to V
IL
(0V), and V
DDQX
for that port must be supplied as
indicated above.
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
Recommended DC Operating
Conditions with V
DDQ
at 3.3V
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
(3)
Ground
Input High Voltage
(Address & Control Inputs)
(3)
Input High Voltage - I/O
(3)
Input Low Voltage
Min.
3.15
3.15
0
2.0
2.0
-0.3
(1)
Typ.
3.3
3.3
0
____
o
Max.
3.45
3.45
0
V
DDQ
+ 150mV
(2)
V
DDQ
+ 150mV
(2)
0.8
Unit
V
V
V
V
V
V
4831 tbl 05b
mA
4831 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+ 150mV for more than 25% of the cycle time or 4ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 150mV.
____
____
NOTES:
1. V
IL >
-1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DDQ
+ 150mV.
3. To select operation at 3.3V levels on the I/Os of a given port, the OPT pin for
that port must be set to V
IH
(3.3V), and V
DDQX
for that port must be supplied as
indicated above.
6.42
5
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