CMOS SyncFIFO
TM
64 x 36
FEATURES:
•
IDT723611
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67MHz
and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers
data from Port A to Port B. The FIFO has flags to indicate empty and full conditions,
and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to
indicate when a selected number of words is stored in memory. Communication
between each port can take place through two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity
is checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
may be used in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
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Free-running CLKA and CLKB may be asynchronous or coincident
(permits simultaneous reading and writing of data on a single clock
edge)
64 x 36 storage capacity
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE) flags
Microprocessor Interface Control Logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Parity
Gen/Check
MBF1
PEFB
PGB
Parity
Generation
Output
Register
RST
ODD/
EVEN
Mail 1
Register
Input
Register
Reset
Logic
RAM
ARRAY
64 x 36
36
A
0
- A
35
Write
Pointer
Read
Pointer
B
0
- B
35
EF
AE
FF
AF
FIFO
Status Flag
Logic
Programmable
Flag Offset
Registers
FS
0
FS
1
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
3024 drw 01
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.
JUNE 2005
DSC-3024/2
©
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT723611
CMOS SyncFIFO
TM
64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
A0-A35
AE
AF
B0-B35
CLKA
CLKB
CSA
CSB
EF
Name
Port-A Data
64 x 36
Almost-Empty Flag
Almost-Full Flag
Port-B Data.
Port-A Clock
Port-B Clock
Port-A Chip Select
Port-B Chip Select
Empty Flag
I/O
I/O
O
O
I/O
I
I
I
I
O
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the
FIFO is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of emptylocations
in the FIFO is less than or equal to the value in the Offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-A and can be asynchron-
ous or coincident to CLKB.
FF
and
AF
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and can be asynchron-
ous or coincident to CLKA.
EF
and
AE
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The
A0-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The
B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
EF
is synchronized to the LOW-to-HIGH transition of CLKB. When
EF
is LOW, the FIFO is empty, and
reads from its memory are disabled. Data can be read from the FIFO to its output register when
EF
is
HIGH.
EF
is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FF
is synchronized to the LOW-to-HIGH/ transition of CLKA. When
FF
is LOW, the FIFO is full, and
writes to its memory are disabled.
FF
is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKA after reset.
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1, which loads one of four
preset values into the Almost-Full and Almost-Empty Offset register (X).
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and a
LOW level selects the FIFO output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
the mail1 register are inhibited while
MBF1
is set LOW.
MBF1
is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH.
MBF1
is set HIGH when the
device is reset.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to
the mail2 register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of
CLKA when a port-A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW. Bytes are organized as
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity genera-
tion is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having
CSA
LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the
PEFA
flag is forced HIGH regardless
of the state of A0-A35 inputs.
When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW. Bytes are organized as
(Port B) B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity
trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
CSB
LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the
PEFB
flag is forced HIGH
regardless of the state of the B0-B35 inputs
4
ENA
ENB
FF
Port-A Enable
Port-B Enable
Full Flag
I
I
O
FS1, FS0
MBA
MBB
MBF1
Flag-Offset Selects
Port-A Mailbox Select
Port-B Mailbox Select
I
I
I
Mail1 Register Flag
O
MBF2
Mail2 Register Flag
O
ODD/
EVEN
PEFA
Odd/Even Parity
Select
Port-A Parity Error
Flag
I
O
(Port A)
PEFB
Port-B Parity Error
Flag
O
JUNE 1, 2005
IDT723611
CMOS SyncFIFO
TM
64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (Continued)
Symbol
PGA
Name
Port-A Parity
Generation
Port-B Parity
Generation
Reset
I/O
Description
I Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity generated
is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and
A27-A35. The generated parity bits are output in the most significant bit of each byte.
I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected
by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35.
The generated parity bits are output in the most significant bit of each byte.
I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while
RST
is LOW. This sets the
AF, MBF1,
and
MBF2
flags HIGH and the
EF, AE,
and
FF
flags
LOW. The LOW-to-HIGH transition of
RST
latches the status of the FS1 and FS0 inputs to select Almost-
Full and Almost-Empty flag offset.
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA isHIGH.
I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
PGB
RST
W/RA
W/RB
Port-A Write/Read
Select
Port-B Write/Read
Select
5
JUNE 1, 2005
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