PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MH
Z
F
ORWARD
E
RROR
C
ORRECTION
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
F
EATURES
•
Clock synthesis of 14/15 or 15/14 of the input reference
clock to be utilized in Forward Error Correction (FEC)
applications
•
Fully integrated PLL
•
2 differential 3.3V LVPECL outputs
•
1 differential clock input pair
•
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVHSTL, LVDS, SSTL, HCSL
•
Output frequency range: 38.88MHz - 700MHz
•
Input frequency range: 36.27MHz - 750MHz
•
VCO range: 200MHz to 700MHz
•
PLL bypass and test modes that support in-circuit testing
and on-chip functional block characterization
•
Cycle-to-cycle jitter: 20ps (typical)
•
Period jitter: TBD
•
Output skew: 10ps (maximum)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8733-01 is a dual output, Differential-
to-3.3V LVPECL Clock Generator and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8733-01 is designed to be used for applica-
tions utilizing Forward Error Correction (FEC) designs. The
ICS8733-01 generates a 14/15 or a 15/14 output clock based
upon the input reference clock in order to incorporate the
FEC capability required by the application.
,&6
Clock generation is performed by a fully integrated and
low-jitter phase-locked loop. The ICS8733-01 accepts any
differential signal as its input with an input reference fre-
quency range of 36.27MHz to 750MHz. There are two
LVPECL outputs which can generate output frequencies of
38.88MHz to 700MHz.
B
LOCK
D
IAGRAM
DIV_SEL0
DIV_SEL1
MR
PLL_SEL
“
N
”
P
IN
A
SSIGNMENT
PLL_SEL
V
CC
V
CC
nc
nc
nc
nc
nc
32 31 30 29 28 27 26 25
nc
FEC_NSEL
0
1
FEC_MSEL
V
EE
÷15
V
EE
TEST_SEL
TEST_EN
V
EE
÷
¼
÷1
÷2
÷4
00
01
10
11
÷14
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
FOUT1
nFOUT1
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
CLK
n_CLK
V
CCA
V
CCA
DIV_SEL0
DIV_SEL1
nc
MR
CLK
nCLK
ICS8733-01
21
20
19
18
17
FEC_NSEL
0
PLL
1
0
1
÷15
0
÷14
“
M
”
1
FOUT0
nFOUT0
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
FEC_MSEL
TEST_SEL
TEST_EN
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8733BY-01
www.icst.com/products/hipercocks.html
1
REV. A JANUARY 17, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MH
Z
F
ORWARD
E
RROR
C
ORRECTION
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
F
UNCTIONAL
D
ESCRIPTION
The ICS8733-01 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
The ICS8733-01 will generate an output having a frequency as follows:
fREF_CLK x M
N
The M and N bits are controlled by the FEC_NSEL and FEC_MSEL control pins as shown in
Table 3A and Table 3B.
As a result, FOUT0 can be configured to have an output frequency equal to 14/15, 15/14, 14/14, or 15/15 of the reference
input frequency.
The second output clock (FOUT1) is configured to produce a frequency equal to FOUT0, FOUT/2, FOUT0/4, or FOUT0x4,
dependent upon the DIV_SEL0 and DIV_SEL1 bits as shown in
Table 3C
and
3D.
The reference input frequency range is dependent upon not only the M and N bits, but also upon the FOUT1 output
configuration which is determined by the DIV_SEL0 and DIV_SEL1 bits.
Table 3C
shows the possible FOUT0 and
FOUT1 output configurations as well as the reference input frequency range for each of these configurations.
The ICS8733-01 also supports in-circuit testing and on-chip functional block characterization via two test inputs and
one test output. With the ICS8733-01 in PLL bypass mode (PLL_SEL = 0), the reference input bypasses the PLL and
in-circuit testing of the N, M, and output dividers can take place.
Table 3D
shows the output configurations for the
different combinations of the DIV_SEL1 and DIV_SEL0 pins.
8733BY-01
www.icst.com/products/hipercocks.html
2
REV. A JANUARY 17, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MH
Z
F
ORWARD
E
RROR
C
ORRECTION
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
Type
Description
No connect.
Pulldown Selects the N divide value. LVCMOS / LVTTL interface levels.
Pulldown Selects the M divide value. LVCMOS / LVTTL interface levels.
Negative supply pins. Connect to ground.
Configures the TEST output pin to one of two different test modes.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown Enables the TEST output pin. LVCMOS / LVTTL interface levels.
Output test pin. Programmed using TEST_SEL pin as shown in Table 3D.
Positive supply pins. Connect to 3.3V.
Differential output for the generator. 3.3V LVPECL interface levels.
Output supply pin. Connect to 3.3V.
Differential ouput for the generator. 3.3V LVPECL interface levels.
Pulldown
Resets the M, N, and output divider. Forces FOUT0 and FOUT1 low.
LVCMOS / LVTTL interface levels.
Determines the output divide value for FOUT1.
Pulldown
LVCMOS / LVTTL interface levels.
Analog supply pins. Connect to 3.3V.
Pullup
Inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 18,
25, 26,
30, 31, 32
2
3
4, 5, 8, 16
6
7
9
10, 28, 29
11, 12
13
14, 15
17
19, 20
21, 22
23
24
27
Name
nc
FEC_NSEL
FEC_MSEL
V
EE
TEST_SEL
TEST_EN
TEST
V
CC
FOUT1,
nFOUT1
V
CCO
FOUT0,
nFOUT0
MR
DIV_SEL1,
DIV_SEL0
V
CCA
nCLK
CLK
PLL_SEL
Unused
Input
Input
Power
Input
Input
Output
Power
Output
Power
Output
Input
Input
Power
Input
Input
Input
Pulldown Non-inver ting differential clock input.
Pullup
Determines whether generator is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
8733BY-01
www.icst.com/products/hipercocks.html
3
REV. A JANUARY 17, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MH
Z
F
ORWARD
E
RROR
C
ORRECTION
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
3B. FEC-MSEL T
RUTH
T
ABLE
N
14
15
FEC_MSEL
0
1
M
15
14
T
ABLE
3A. FEC_NSEL T
RUTH
T
ABLE
FEC_NSEL
0
1
T
ABLE
3C. O
UTPUT
C
ONFIGURATION
AND
I
NPUT
F
REQUENCY
R
ANGE
T
ABLE
Maximum
Minimum Maximum Minimum Maximum
Input
FOUT0
FOUT0
FOUT1
FOUT1
Frequency
(MHz)
(MHz)
(MHz)
(MHz)
(MHz)
81.67
87.5
87.5
93.75
326.67
350
350
375
653.33
700
700
750
653.33
700
700
750
38.86
36.27
38.88
36.29
100
100
100
100
200
200
200
200
200
200
200
200
87.50
87.50
87.50
87.50
350
350
350
350
700
700
700
700
700
700
700
700
155.44
145.08
155.52
145.15
100
100
100
100
100
100
100
100
50
50
50
50
350
350
350
350
350
350
350
350
350
350
350
350
175
175
175
175
Reference Input Frequency Range (MHz)
Minimum
Input
DIV_SEL1 DIV_SEL0 FEC_NSEL FEC_MSEL
Frequency
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
36.27
36.27
38.88
38.88
93.3
100
100
107
186.7
200
200
214.3
186.7
200
200
214.3
T
ABLE
3D. O
UTPUT
C
ONFIGURATION
T
ABLE
DIV_SEL1
0
0
1
1
DIV_SEL0
0
1
0
1
AND
T
EST
M
ODE
O
PERATION
PLL_SEL = 0 and TEST_EN = 1
FOUT0
fREF/4N
fREF/N
fREF/N
fREF/N
FOUT1
fREF/N
fREF/N
fREF/2N
fREF/4N
TEST
TEST_SEL = 0
2fREF/N
2fREF/N
fREF/N
fREF/N
TEST
TEST_SEL = 1
fREF/2MN
2fREF/MN
fREF/MN
fREF/MN
PLL_SEL = 1
FOUT0
fREFxM/N
fREFxM/N
fREFxM/N
fREFxM/N
FOUT1
fREFx4M/N
fREFxM/N
fREFx2M/N
fREFx4M/N
NOTE: In bypass mode, FOUT0 and FOUT1 will not always result in a 50% duty cycle.
Test output will never be 50% duty cycle.
8733BY-01
www.icst.com/products/hipercocks.html
4
REV. A JANUARY 17, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MH
Z
F
ORWARD
E
RROR
C
ORRECTION
D
IFFERENTIAL
-
TO
-3.3V LVPECL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
CC
Outputs, V
CCO
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
X
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC
Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
FEC_NSEL, FEC_MSEL,
TEST_SEL, TEST_EN,
DIV_SELx, PLL_SEL, MR
FEC_NSEL, FEC_MSEL,
TEST_SEL, TEST_EN,
DIV_SELx, PLL_SEL, MR
FEC_NSEL, FEC_MSEL,
TEST_SEL, TEST_EN,
DIV_SELx, MR
PLL_SEL
FEC_NSEL, FEC_MSEL,
TEST_SEL, TEST_EN,
DIV_SELx, MR
PLL_SEL
Test Conditions
Minimum
2
Typical
Maximum
V
CC
+ 0.3
Units
V
V
IL
-0.3
0.8
V
I
IH
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
150
5
µA
µA
µA
µA
V
I
IL
Input
Low Current
Output
TEST; NOTE 1
2.6
High Voltage
Output
V
OL
TEST; NOTE 1
Low Voltage
NOTE 1: Outputs terminated with 50Ω to V
CCO
/2. See page 7, Figure 1, 3.3V Output Load Test Circuit.
V
OH
0.5
V
8733BY-01
www.icst.com/products/hipercocks.html
5
REV. A JANUARY 17, 2002
嵌入式系统
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