SINGLE CHANNEL 0.7V DIFFERENTIAL-
TO-LVTTL TRANSCEIVER
ICS8512061I
Features
•
•
•
•
•
•
•
•
•
One HCSL output pair and one LVCMOS/LVTTL output
One single-ended LVCMOS/LVTTL signal input
LVTTL I/O signal: up to 250MHz
HCSL interface pins in high impedance state when the device is
powered down
Power-up and power-down glitch-free
Additive Phase Jitter, RMS: 0.23ps (typical)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
General Description
ICS
HiPerClockS™
The ICS8512061I is a transceiver which can
interchange data across multipoint data bus
structures.
The device has an LVTTL driver and one HCSL
receiver driver. It translates between LVTTL signals
and HCSL signals.
Applications
Backplane Transmission
Telecommunication System
Data Communications
ATCA Clock Distribution
Block Diagram
Pin Assignment
GND
QB
DIR_SEL
IN
1
2
3
4
8
7
6
5
QA
nQA
V
DD
IREF
QB
IREF
HCSL
Interface
QA
ICS8512061I
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
IN
Pullup
nQA
DIR_SEL
Pulldown
IDT™ / ICS™
TRANSCEIVER
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ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 8
Name
GND
QB
DIR_SEL
IN
IREF
V
DD
nQA, QA
Power
Output
Input
Input
Input
Power
Output
Pulldown
Pullup
Type
Description
Power supply ground.
Single-ended output. LVCMOS/LVTTL interface levels.
HCSL receiver and driver direction select pin. When HIGH, selects the
IN-to-QA/nQA path. When LOW, selects the QA/nQA-to-QB path.
LVCMOS/LVTTL interface levels.
Single-ended signal input. LVCMOS/LVTTL interface levels.
An external fixed precision resistor (475
Ω
) from this pin to ground provides a
reference current used for differential current-mode QA/nQA outputs.
Power supply pin.
Differential transceiver pair. HCSL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QB
V
DD
= 3.6V
Test Conditions
Minimum
Typical
4
8
51
51
20
Maximum
Units
pF
pF
k
Ω
k
Ω
Ω
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
129.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
20
Units
V
mA
IDT™ / ICS™
TRANSCEIVER
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ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
IN
Input High Current
DIR_SEL
IN
I
IL
V
OH
V
OL
Input Low Current
DIR_SEL
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
QB
QB
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V
V
DD
= 3.6V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
NOTE: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
Table 3C. Differential DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
PP
V
CMR
Parameter
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
DIR_SEL = 0
DIR_SEL = 0
Minimum
0.15
GND + 0.5
Typical
Maximum
1.3
V
DD
– 0.85
Units
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
AC Electrical Characteristics
Table 4A. LVTTL (QB) Output Mode, Receiver AC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
F
MAX
t
PD
tjit
t
R
/t
F
odc
Parameter
Output Frequency
Propagation Delay, NOTE 1
Buffer Additive Phase Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle
QA/nQA to QB
100MHz, Integration Range: 12kHz
– 20MHz
20% - 80%
200
40
1.7
0.23
700
60
Test Conditions
Minimum
Typical
Maximum
250
2.5
Units
MHz
ns
ps
ps
%
NOTE 1: Measured from V
DD
/2 input cross point to the output at V
DD
/2.
IDT™ / ICS™
TRANSCEIVER
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ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 4B. HCSL (QA/nQA) AC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Parameter
f
MAX
tjit
t
PD
Rise
Edge Rate
Fall
Edge Rate
V
rb
V
MAX
V
MIN
V
CROSS
∆V
CROSS
odc
Symbol
Output Frequency
Buffer Additive Phase Jitter, RMS
Propagation Delay, NOTE 1
Rising Edge Rate; NOTE 2, 3
Falling Edge Rate; NOTE 2, 3
Ringback Voltage; NOTE 2, 4
Absolute Max Output Voltage;
NOTE 5, 6
Absolute Min Output Voltage;
NOTE 5, 7
Absolute Crossing Voltage;
NOTE 5, 8, 9
Total Variation of V
CROSS
over all
edges; NOTE 5, 8, 10
Output Duty Cycle; NOTE 11
45
-300
250
550
140
55
100MHz, Integration Range:
12kHz – 20MHz
IN to QA/nQA
1.1
0.6
0.6
-100
0.29
1.7
4.0
4.0
100
1150
Test Conditions
Minimum
Typical
Maximum
250
Units
MHz
ps
ns
V/ns
V/ns
V
mV
mV
mV
mV
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 input cross point to the differential output crossing point.
NOTE 2: Measurement taken from differential waveform.
NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from QA minus nQA). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero
crossing.
NOTE 4: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it
is allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of QA equals the Falling edge of nQA.
See Parameter Measurement Information Section
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of Rising QA and Falling nQA. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11: Input duty cycle must be 50%.
IDT™ / ICS™
TRANSCEIVER
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ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Additive Phase Jitter (HCSL)
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.29ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™
TRANSCEIVER
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ICS8512061AGI REV. B NOVEMBER 19, 2008
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