Low Skew, 1-to-4 Multiplexed Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer
ICS8305
DATA SHEET
General Description
The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock
inputs that accept either differential or single ended input levels. The
clock enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
Four LVCMOS / LVTTL outputs, 7
output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
•
Block Diagram
CLK_EN
Pullup
D
Q
LE
LVCMOS_CLK
Pulldown
CLK
Pulldown
nCLK
Pullup/
Pulldown
Pin Assignment
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
0
0
Q0
1
1
Q1
CLK_SEL
Pullup
Q2
ICS8305
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm package body
G Package
Top View
Q3
OE
Pullup
ICS8305AGI REVISION C SEPTEMBER 17, 2012
1
©2012 Integrated Device Technology, Inc.
ICS8305 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
4
5
6
7
8
10, 12, 14, 16
11, 15
Name
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
Q3, Q2, Q1, Q0
V
DDO
Power
Input
Power
Input
Input
Input
Input
Input
Output
Power
Pullup
Pulldown
Pullup/
Pulldown
Pullup
Pulldown
Pullup
Type
Description
Power supply ground
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Power supply pin.
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7
output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
11
7
Maximum
Units
pF
k
k
pF
ICS8305AGI REVISION C SEPTEMBER 17, 2012
2
©2012 Integrated Device Technology, Inc.
ICS8305 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3. Control Input Function Table
Inputs
OE
1
1
1
1
0
CLK_EN
0
0
1
1
X
CLK_SEL
0
1
0
1
X
Selected Source
LVCMOS_CLK
CLK/nCLK
LVCMOS_CLK
CLK/nCLK
Outputs
Q0:Q3
Disabled; Low
Disabled; Low
Enabled
Enabled
Hi-Z
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
Disabled
nCLK
CLK,
LVCMOS_CLK
Enabled
CLK_EN
Q0:Q3
Figure 1. CLK_EN Timing Diagram
ICS8305AGI REVISION C SEPTEMBER 17, 2012
3
©2012 Integrated Device Technology, Inc.
ICS8305 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
89C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5% or 2.5V±5% or 1.8V±0.5V or 1.5V±5%,
T
A
= 0°C to 70°C
Symbol
V
DD
Parameter
Positive Supply Voltage
Test Conditions
Minimum
3.135
3.135
2.375
V
DDO
Output Supply Voltage
1.65
1.425
I
DD
I
DDO
Power Supply Current
Output Supply Current
1.8
1.5
1.95
1.575
21
5
V
V
mA
mA
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
Units
V
V
V
ICS8305AGI REVISION C SEPTEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
ICS8305 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4B. LVCMOS/LVTTL DC Characteristics,
T
A
= 0°C to 70°C
Symbol
Parameter
Input High
Voltage
CLK_EN,
CLK_SEL, OE
LVCMOS_CLK
Input Low
Voltage
CLK_EN,
CLK_SEL, OE
LVCMOS_CLK
Input
High Current
CLK_EN,
CLK_SEL, OE
LVCMOS_CLK
Input
Low Current
CLK_EN,
CLK_SEL, OE
LVCMOS_CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
V
DDO
= 1.5V ± 5%
V
DDO
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
V
DDO
= 1.5V ± 5%
I
OZL
I
OZH
Output Hi-Z Current Low
Output Hi-Z Current High
-5
5
-150
-5
2.6
1.8
1.5
V
DDO
- 0.3
0.5
0.5
0.4
0.35
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
V
V
µA
µA
V
IH
V
IL
I
IH
I
IL
NOTE 1: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
Table 4C. Differential DC Characteristics,
T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
ICS8305AGI REVISION C SEPTEMBER 17, 2012
5
©2012 Integrated Device Technology, Inc.
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