October 2003
rev 1.0
Features
Generates an EMI optimized clocking
signal at output.
Input frequency – 14.31818 MHz.
Frequency outputs:
o
o
120 MHz (modulated) - default.
72 MHz (modulated) or 48
(modulated) selectable via I2C
MHz
ASM3P2508A
spread the bandwidth of a synthesized clock, thereby
decreasing the peak amplitudes of its harmonics. This
results in significantly lower system EMI compared to the
typical narrow band signal produced by oscillators and
most clock generators. Lowering EMI by increasing a
signal’s bandwidth is called spread spectrum clock
generation.
The ASM3P2508A has a feature to power down the
72MHz / 48MHz output by writing data into specific
registers in the device via I2C. By writing a ‘0’ into bit 1 of
byte 0, the PLL block generating 72MHz/48MHz can be
powered down. A ‘0’ into bit ‘7’ of byte 1 selects an output
of 72MHz on FOUT2CLK while a ‘1’ at the same location
selects a 48MHz clock output. However, the I2C block,
crystal oscillator, and the PLL block generating 120MHz
would be always running.
± 1% Centre spread.
Modulation rate: 40 KHz.
Supply voltage range 3.3V (± 0.3V).
Available in 8-pin TSSOP package.
Commercial and Industrial Temperature
range.
Product Description
The ASM3P2508A is a versatile spread spectrum
frequency
modulator.
The
ASM3P2508A
reduces
electromagnetic interference (EMI) at the clock source.
The ASM3P2508A allows significant system cost savings
by reducing the number of circuit board layers and
shielding that are required to pass EMI regulations. The
ASM3P2508A modulates the output of PLL in order to
Block Diagram
V
DD
XIN
XOUT
Crystal
Oscillator
PLL 1
FOUT1CLK
(120 MHz)
SCL
SDA
I2C
Interface
PLL 2
FOUT2CLK
(72 MHz / 48 MHz)
V
SS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara CA
•
Tel: 408-855-4900
•
Fax: 408-855-4999
•
www.alsc.com
October 2003
rev 1.0
Pin Configuration
XIN
XOUT
V
DD
FOUT1CLK
1
2
8
7
ASM3P2508A
V
SS
SCL
SDA
FOUT2CLK
ASM3P2508A
3
4
6
5
Pin Description
Pin Name
XIN
XOUT
V
DD
FOUT1CLK
FOUT2CLK
SDA
SCL
V
SS
Type
I
O
P
O
O
I/O
I
P
Description
Connection to crystal
Connection to crystal
Power supply for the analog and digital blocks
Clock output-1 (120 MHz)
Clock output-2 ( 72 MHz / 48 MHz)
I2C Data
I2C Clock
Ground to entire chip
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October 2003
rev 1.0
Absolute Maximum Ratings
Symbol
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
ASM3P2508A
Parameter
Rating
Unit
Supply voltage, DC
(V
SS
– 0.5) to 7
V
Input voltage, DC
(V
SS
-0.5) to (V
DD
+0.5)
V
Output voltage, DC
(V
SS
-0.5) to (V
DD
+ 0.5)
V
Input clamp current (V
I
<0 or V
I
>V
DD
)
-50 to +50
mA
Output clamp current (V
I
<0 or V
I
>V
DD
)
-50 to +50
mA
Storage temperature
-65 to +125
°C
Ambient temperature range, under bias
-55 to 125
°C
Junction temperature
150
°C
Lead temperature (soldering 10 sec)
260
°C
Input static discharge voltage protection
2
kV
(MIL –STD 883E, Method 3015.7)
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Operating Conditions
Parameter
Supply Voltage
Ambient Operating
Temperature
Range
Crystal Resonator
Frequency
Output Driver Load
Capacitance
Symbol
V
DD
T
A
F
XIN
C
L
Condition / Description
3.3V ± 10%
Min
3
-40
14.31818
15
Typ
3.3
Max
3.6
+85
Unit
V
°C
MHz
pF
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October 2003
rev 1.0
DC Electrical Characteristics
Parameter
Symbol
Conditions / Description
Overall
V
DD
=3.3V, F
CLK
=14.31818MHz,
Supply Current,
I
DD
Dynamic
C
L
=15pF
V
DD
= 3.3V, Software Power
Supply Current,
I
DDL
Static
Down
All input pins
High-Level Input
V
DD
=3.3V
V
IH
Voltage
Low-Level Input
V
DD
=3.3V
V
IL
Voltage
High-Level Input
I
IH
Current
Low-Level Input
I
IL
Current (pull-up)
High-Level Output
V
DD
=V(XIN) = 3.3V, V
O
=0V
I
xOH
Source Current
Low-Level Output
V
DD
=3.3V, V(XIN)=V
O
=5.5V
I
xOL
Source Current
Clock Outputs (FOUT1CLK, FOUT2CLK)
High-Level Output
V
O
=2.4V
I
OH
Source Current
Low-Level Output
V
O
=0.4V
I
OL
Sink Current
Output Impedance
V
O
=0.5V
DD
; output driving high
Z
OH
Z
OL
Vo=0.5V
DD
; output driving low
AC Electrical Characteristics
Parameter
Rise Time
Fall Time
Clock Duty
Cycle
Clock
Stabilization
Time
Symbol
t
r
t
f
Conditions/ Description
V
O
= 0.3V to 3.0V; CL = 15pF
V
O
= 3.0V to 0.3V; CL = 15pF
Ratio of pulse width (as
measured from rising edge to
next falling edge at 2.5V) to one
clock period
Output active from power up,
RUN Mode via Software Power
Down
Min
Typ
2.1
1.9
Max
Min
Typ
43
tbd
2.0
V
SS
-0.3
-1
-20
10
-10
-36
21
-21
-20
23
29
27
ASM3P2508A
Max
Unit
mA
mA
V
DD
+0.3
0.8
1
-80
30
-30
V
V
µ
A
µ
A
mA
mA
mA
mA
Ω
Unit
ns
ns
%
45
55
t
STB
125
us
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rev 1.0
General I2C Serial Interface Information
The information in this section assumes familiarity
with I2C programming.
How to Write through I2C:
•
•
•
•
•
•
•
•
•
•
Master (host) sends a start bit.
Master (host) sends the write address XX (H)
ASM3P2508A device will acknowledge
Master (host) sends the beginning byte location
(=N)
ASM3P2508A device will acknowledge
Master (host) sends a dummy byte count
ASM3P2508A device will acknowledge
Master (host) starts sending byte N through
byte N+X – 1*
ASM3P2508A device will acknowledge each
byte one at a time.
Master (host) sends a Stop bit
Controller (Host)
Start Bit
Slave Address XX(H)
ACK
Beginning byte
location (=N)
ACK
Dummy byte count
ACK
Beginning byte
(Byte N)
ACK
Next Byte (Byte N+1)
ACK
-------
----
Last Byte
(Bye N+X-1)
ACK
Stop Bit
ACK
ASM3P2508A
(slave/receiver)
How to Read through I2C:
•
•
•
•
•
•
•
•
•
•
•
•
•
ASM3P2508A
Master (host) will send start bit.
Master (host) sends the write address XX (H)
ASM3P2508A device will acknowledge
Master (host) sends the beginning byte location
(=N)
ASM3P2508A device will acknowledge
Master (host) will send a separate start bit
Master (host) sends the read address XX (H)
ASM3P2508A device will acknowledge
ASM3P2508A device will send the dummy byte
count
Master (host) acknowledges
ASM3P2508A device sends byte N through
byte N+X – 1*
Master (host) will need to acknowledge each
byte
Master (host) will send a stop bit
(* X is the number of bytes)
Controller (Host)
ASM3P2508A
(slave/receiver)
Start Bit
Slave Address XX(H)
ACK
Beginning Byte = N
ACK
Repeat start
Slave address
ACK
Dummy Byte Count
Beginning byte N
ACK
Next Byte N+1
ACK
----
-------
Last Byte (Byte N+X-1)
Not Acknowledge
Stop Bit
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