WF128K32-XXX5
HI-RELIABILITY PRODUCT
128K
X
32 5V FLASH MODULE, SMD 5962-94716
FEATURES
s
Access Times of 50*, 60, 70, 90, 120, 150ns
s
Packaging:
• 66 pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
• 68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP
(Package 502)
• 68 lead, Hermetic CQFP, 22.4mm (0.880 inch) square.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint.
– G2 (Package 500), 5.08mm (0.200 inch) high
– G2U (Package 510), 3.56mm (0.140 inch) high
s
Sector Architecture
• 8 equal size sectors of 16KBytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s
100,000 Erase/Program Cycles Typical, 0°C to +70°C
s
Organized as 128Kx32
s
Commercial, Industrial and Military Temperature Ranges
s
5 Volt Programming. 5V
±
10% Supply
s
Low Power CMOS, 1mA Standby Typical
s
Embedded Erase and Program Algorithms
s
TTL Compatible Inputs and CMOS Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
s
Page Program Operation and Internal Program Control Time
s
Weight
WF128K32-XG2X5 - 8 grams typical
WF128K32-XG2UX5 - 8 grams typical
WF128K32-XH1X5 - 13 grams typical
WF128K32-XG4TX5 - 20 grams typical
Note: For programming information refer to Flash Programming 1M5
Application Note.
* The access time of 50ns is available in Industrial and Commercial
temperature ranges only.
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
NC
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WF128K32N-XH1X5
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
NC
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
4
A
5
A
6
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
OE
A
0-16
WE
1
CS
1
PIN DESCRIPTION
56
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
I/O
22
128K x 8
128K x 8
128K x 8
128K x 8
I/O
21
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
June 2000 Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 2
PIN CONFIGURATION FOR WF128K32-XG4TX5
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-16
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
WE
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
CS
1-4
OE
V
CC
GND
NC
BLOCK DIAGRAM
CS
1
WE
OE
A
0
-
16
128K x 8
128K x 8
CS
2
CS
3
CS
4
128K x 8
128K x 8
8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
NC
NC
NC
NC
NC
NC
NC
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
FIG. 3
PIN CONFIGURATION FOR WF128K32-XG2X5 (Dual Cavity)
AND WF128K32-XG2UX5 (Single Cavity)
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-16
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CS
1
CS
2
NC
WE
2
WE
3
WE
4
V
CC
OE
A
11
A
12
A
13
A
14
A
15
A
16
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
WE
1-4
CS
1-4
OE
0.940"
V
CC
GND
NC
The White 68 lead G2/G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2/G2U has the
TCE and lead inspection advan-
tage of the CQFP form.
WE
1
CS
1
A
0-16
BLOCK DIAGRAM
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
NC
NC
NC
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WF128K32-XXX5
ABSOLUTE MAXIMUM RATINGS (1)
Parameter
Operating Temperature
Supply Voltage Range (V
CC
)
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
Endurance (write/erase cycles) Mil Temp
A
9
Voltage for sector protect (V
ID
) (3)
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
10 years
10,000 cycles min.
-2.0 to +14.0
V
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G4T
CQFP G2
CQFP G2U
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
Unit
°C
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
A
9
Voltage for Sector Protect
Symbol
V
CC
V
IH
V
IL
T
A
V
ID
Min
4.5
2.0
-0.5
-55
11.5
Max
5.5
V
CC
+ 0.3
+0.8
+125
12.5
Unit
V
V
V
°C
V
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
50
20
15
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot V
SS
to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is V
CC
+ 0.5V. During voltage transitions,
outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A
9
pin is -0.5V. During voltage transitions, A
9
may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A
9
is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS - CMOS COMPATIBLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program
or Erase (2)
V
CC
Standby Current
V
CC
Static Current
Output Low Voltage
Output High Voltage
Output High Voltage
Low V
CC
Lock Out Voltage
Symbol
I
LI
I
LOx32
I
CC1
I
CC2
I
CC3
I
CC4
V
OL
V
OH1
V
OH2
V
LKO
Conditions
Min
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IL
, OE = V
IH
CS = V
IL
, OE = V
IH
V
CC
= 5.5, CS = V
IH
, f = 5MHz
V
CC
= 5.5, CS = V
IH
I
OL
= 8.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
I
OH
= -100
µA,
V
CC
= 4.5
0.85 x
V
CC
V
CC
-0.4
3.2
Max
10
10
140
200
6.5
0.6
0.45
µA
µA
mA
mA
mA
mA
V
V
V
V
Unit
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle Time
WE Setup Time
CS Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
Symbol
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHWH
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
WH
t
CPH
50
0
25
0
25
0
40
0
20
14
2.2
0
12.5
60
-50
Min
Max
Min
60
0
30
0
30
0
45
0
20
14
2.2
0
12.5
60
-60
Max
70
0
35
0
30
0
45
0
20
14
2.2
0
12.5
60
-70
Min Max
90
0
45
0
45
0
45
0
20
14
2.2
0
12.5
60
-90
Min
Max
-120
Min
120
0
50
0
50
0
50
0
20
14
2.2
0
12.5
60
Max
-150
Min
150
0
50
0
50
0
50
0
20
14
2.2
0
12.5
60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
sec
Unit
FIG. 4
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Symbol
-50
Min
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (min)
Sector Erase Time
Read Recovery Time Before Write
V
CC
Setup Time
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
1. For Toggle and Data Polling.
t
OES
t
OEH
0
10
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHEH
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
CH
t
WPH
50
0
25
0
25
0
40
0
20
14
2.2
0
50
12.5
0
10
60
Max
Min
60
0
30
0
30
0
45
0
20
14
2.2
0
50
12.5
0
10
60
-60
Max
-70
Min
70
0
35
0
30
0
45
0
20
14
2.2
0
50
12.5
0
10
60
Max
-90
Min
90
0
45
0
45
0
45
0
20
14
2.2
0
50
12.5
0
10
60
Max
-120
Min
120
0
50
0
50
0
50
0
20
14
2.2
0
50
12.5
0
10
60
Max
-150
Min
150
0
50
0
50
0
50
0
20
14
2.2
0
50
12.5
60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
µs
sec
ns
ns
Unit
AC CHARACTERISTICS – READ ONLY OPERATIONS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
Output Hold from Address, CS or OE Change,
whichever is first
1. Guaranteed by design, not tested.
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
50
50
50
25
20
20
0
-50
Min
Max
60
60
60
30
20
20
0
-60
Min
Max
-70
Min
70
70
70
35
20
20
0
Max
90
90
90
40
25
25
0
-90
Min Max
-120
Min
120
120
120
50
30
30
0
Max
-150
Min
150
150
150
55
35
35
Max
ns
ns
ns
ns
ns
ns
ns
Unit
5
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