The ASM2P3807A 3.3V clock driver is built using advanced
dual metal CMOS technology. This low skew clock driver
offers 1:10 fanout. The large fanout from a single input
reduces loading on the preceding driver and provides an
efficient clock distribution network. The ASM2P3807A
offers low capacitance inputs with hysteresis for improved
noise margins. Multiple power and grounds reduce noise.
Typical applications are clock and signal distribution.
Block Diagram
O1
O2
O3
O4
O5
IN
O6
O7
O8
O9
O10
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
January 2006
rev 0.2
Pin Configuration
IN
GND
O
1
V
CC
O
2
GND
O
3
V
C
C
ASM2P3807A
1
2
3
4
5
6
7
8
9
10
20
19
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
O
4
GND
A
S
M
2
P
3
8
0
7
A
18
17
16
15
14
13
12
11
SOIC / SSOP/ QSOP Packages
TOP VIEW
Pin Description
Pin#
1
3,5,7,9,11,12,14,16,18,19
2,6,10,13,17
4,8,15,20
Pin Names
IN
O 1-O10
GND
Vcc
Description
Clock Inputs
Clock Outputs
Ground
Power
Absolute Maximum Ratings
Symbol
V
TERM1
V
TERM2
V
TERM3
T
STG
I
OUT
device reliability.
NOTES:
1. V
CC
terminals.
2. Input terminals.
3. Outputs and I/O terminals.
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
2 of 19
January 2006
rev 0.2
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
ASM2P3807A
Parameter
1
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
4.5
5.5
Max
6
8
Unit
pF
pF
Note:1. This parameter is measured at characterization but not tested.
Power Supply Characteristics
Symbol
∆I
CC
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Test Conditions
1
V
CC
= Max.
V
IN
= V
CC
–0.6V
3
V
CC
= Max.
Min
-
Typ
2
10
Max
30
Unit
µA
I
CCD
Dynamic Power Supply
Current
4
Input toggling
50% Duty Cycle
Outputs Open
V
CC
= Max.
Input toggling
V
IN
= V
CC
V
IN
= GND
-
0.31
0.45
mA/
MHz
I
C
Total Power Supply Current
5
50% Duty Cycle
Outputs Open
fi = 50MHz
V
IN
= V
CC
V
IN
= GND
-
35
50
mA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
CC
-0.6V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. I
C
= IQUIESCENT + IINPUTS + IDYNAMIC
I
C
= I
CC
+
∆I
CC
DHNT + I
CCD
(fi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
-0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
3 of 19
January 2006
rev 0.2
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Commercial: T
A
= 0°C to +70°C, Industrial: TA = -40°C to +85°C, V
CC
= 3.3V ± 0.3V
ASM2P3807A
Symbol
V
IH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedence Output Current
(3-State Output Pins)
Clamp Diode Voltage
Output HIGH Current
Test Conditions
1
Guaranteed Logic HIGH Level
Min
2
2
Typ
-
-
-
-
-
-
-
-
-
-0.7
-60
Max
5.5
V
CC
+ 0.5
0.8
±1
±1
±1
±1
±1
±1
-1.2
-110
Unit
V
V
IL
Guaranteed Logic LOW Level
V
CC
= Max
V
I
= 5.5V
V
I
= V
CC
V
CC
= Max
V
I
= GND
V
I
= GND
V
CC
= Max
V
O
= V
CC
V
O
= GND
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
,
V
O
= 1.5V
3
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
,
V
O
= 1.5V
3
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –0.1mA
I
OH
= –8mA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
-0.5
-
-
-
-
-
-
-
-36
V
I
IH
µA
I
IL
I
OZH
I
OZL
V
IK
I
ODH
µA
V
mA
I
ODL
V
OH
Output LOW Current
Output HIGH Voltage
50
V
CC-
0.2
2.4
5
-
-
-
-
-60
-
90
-
3
-
0.2
0.3
-
-135
150
0.1
200
-
-
0.2
0.4
0.5
±1
-240
-
10
mA
V
V
OL
Output LOW Voltage
V
CC
= Min
V
IN
= V
IH
or V
IL
V
I
OFF
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Input Power Off Leakage
Short Circuit Current
4
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
= 4.5V
V
CC
= Max., V
O
= GND
3
-
V
CC
= Max.
V
IN
= GND or V
CC
µA
mA
mV
µA
-
NOTES:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested
.
5. V
OH
= Vcc - 0.6V at rated current.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
4 of 19
January 2006
rev 0.2
Switching Characteristics Over Operating Range – Commercial
3,4
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK(O)
Output Rise Time
Output Fall Time
Output skew: skew
between outputs of
same package (same
transition)
Pulse skew: skew
between opposite
transitions of same
output (|t
PHL
– t
PLH
|)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package type and
speed grade
ASM2P3807A
Parameter
Propagation Delay
Conditions
1
50Ω to V
CC
/2
C
L
= 10pF
(See figure 1)
or 10Ω AC
termination,
C
L
= 50pF
(See figure 2)
f≤ 100MHz
Outputs
connected in
groups of two
Min
1.5
-
-
-
2
ASM2P3807A
Max
3
1.5
1.5
0.35
Unit
nS
nS
nS
nS
t
SK(P)
-
0.35
nS
t
SK(T)
-
0.65
nS
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
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