INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4093B
gates
Quadruple 2-input NAND Schmitt
trigger
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple 2-input NAND Schmitt trigger
DESCRIPTION
The HEF4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a two-input NAND gate with
Schmitt-trigger action on both inputs. The gate switches at
different points for positive and negative-going signals.
The difference between the positive voltage (V
P
) and the
negative voltage (V
N
) is defined as hysteresis voltage
(V
H
).
HEF4093B
gates
Fig.2 Pinning diagram.
HEF4093BP(N):
HEF4093BD(F):
HEF4093BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
Quadruple 2-input NAND Schmitt trigger
DC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C
V
DD
V
Hysteresis
voltage
Switching levels
positive-going
input voltage
negative-going
input voltage
5
10
15
5
10
15
5
10
15
V
N
V
P
V
H
SYMBOL
MIN.
0,4
0,6
0,7
1,9
3,6
4,7
1,5
3
4
TYP.
0,7
1,0
1,3
2,9
5,2
7,3
2,2
4,2
6,0
−
−
−
3,5
7
11
3,1
6,4
10,3
HEF4093B
gates
MAX.
V
V
V
V
V
V
V
V
V
Fig.5
Fig.4 Transfer characteristic.
Waveforms showing definition of
V
P
, V
N
and V
H
; where V
N
and V
P
are
between limits of 30% and 70%.
January 1995
3
Philips Semiconductors
Product specification
Quadruple 2-input NAND Schmitt trigger
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
5
10
15
5
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PLH
t
PHL
SYMBOL
TYP.
90
40
30
85
40
30
60
30
20
60
30
20
MAX.
185 ns
80 ns
60 ns
170 ns
80 ns
60 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
HEF4093B
gates
TYPICAL EXTRAPOLATION
FORMULA
63 ns
+
(0,55 ns/pF) C
L
29 ns
+
(0,23 ns/pF) C
L
22 ns
+
(0,16 ns/pF) C
L
58 ns
+
(0,55 ns/pF) C
L
29 ns
+
(0,23 ns/pF) C
L
22 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
1300 f
i
+ ∑(f
o
C
L
)
×
V
DD2
6400 f
i
+ ∑(f
o
C
L
)
×
V
DD2
18 700 f
i
+ ∑(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
Quadruple 2-input NAND Schmitt trigger
HEF4093B
gates
Fig.6
Typical drain current as a function of input
voltage; V
DD
= 5 V; T
amb
= 25
°C.
Fig.7
Typical drain current as a function of input
voltage; V
DD
=10 V; T
amb
= 25
°C.
Fig.8
Typical drain current as a function of input
voltage; V
DD
= 15 V; T
amb
= 25
°C.
January 1995
5
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