INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4521B
MSI
24-stage frequency divider and
oscillator
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
DESCRIPTION
The HEF4521B consists of a chain of 24 toggle flip-flops
with an overriding asynchronous master reset input (MR),
and an input circuit that allows three modes of operation.
The single inverting stage (I
2
/O
2
) will function as a crystal
oscillator, or in combination with I
1
as an RC oscillator, or
as an input buffer for an external oscillator. Low-power
HEF4521B
MSI
operation as a crystal oscillator is enabled by connecting
external resistors to pins 3 (V
SS
’) and 5 (V
DD
’).
Each flip-flop divides the frequency of the previous flip-flop
by two, consequently the HEF4521B will count up to
2
24
= 16777216. The counting advances on the HIGH to
LOW transition of the clock (I
2
). The outputs of the last
seven stages are available for additional flexibility.
Fig.1 Functional diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
COUNT CAPACITY
HEF4521B
MSI
OUTPUT
O
18
O
19
O
20
O
21
Fig.2 Pinning diagram.
O
22
O
23
O
24
HEF4521BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4521BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
COUNT CAPACITY
2
18
= 262 144
2
19
= 524 288
2
20
= 1 048 576
2
21
= 2 097 152
2
22
= 4 194 304
2
23
= 8 388 608
2
24
= 16 777 216
FUNCTIONAL TEST SEQUENCE
INPUTS
MR
H
I
2
L
O
2
L
CONTROL
TERMINALS
V
SS
’
V
DD
V
DD
’
V
SS
OUTPUTS
REMARKS
O
18
to O
24
L
counter is in three 8-stage sections
in parallel mode; I
2
and O
2
are
interconnected (O
2
is now input);
counter is reset by MR
255 pulses are clocked into I
2
, O
2
(the counter advances on the LOW
to HIGH transition)
V
SS
’ is connected to V
SS
the input I
2
is made HIGH
V
DD
’ is connected to V
DD
; O
2
is
now made floating and becomes an
output; the device is now in the
2
24
mode
counter ripples from an all HIGH
state to an all LOW state
L
V
DD
V
SS
H
L
L
L
L
H
H
L
L
L
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
H
H
H
L
V
SS
V
DD
L
A test function has been included for the reduction of the
test time required to exercise all 24 counter stages. This
test function divides the counter into three 8-stage
sections by connecting V
SS
’ to V
DD
and V
DD
’ to V
SS
. Via
I
2
(connected to O
2
) 255 counts are loaded into each of
the 8-stage sections in parallel. All flip-flops are now at a
HIGH state.
The counter is now returned to the normal 24-stage in
series configuration by connecting V
SS
’ to V
SS
and V
DD
’ to
V
DD
. One more pulse is entered into input I
2
, which will
cause the counter to ripple from an all HIGH state to an all
LOW state.
January 1995
3
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January 1995
4
Fig.3 Logic diagram; for schematic diagram of clock circuit see Fig.4.
Philips Semiconductors
24-stage frequency divider and oscillator
HEF4521B
MSI
Product specification
Philips Semiconductors
Product specification
24-stage frequency divider and oscillator
HEF4521B
MSI
Fig.4 Schematic diagram of clock input circuitry.
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
2
→
O
18
HIGH to LOW
5
10
15
5
LOW to HIGH
O
n
→
O
n
+
1
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
MR
→
O
n
HIGH to LOW
I
1
→
O
1
HIGH to LOW
10
15
5
10
15
5
10
15
5
LOW to HIGH
10
15
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
950
350
220
950
350
220
40
15
10
40
15
10
120
55
40
90
35
25
60
30
20
1900
700
440
1900
700
440
80
30
20
80
30
20
240
110
80
180
70
50
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
923 ns
+
(0,55 ns/pF) C
L
339 ns
+
(0,23 ns/pF) C
L
212 ns
+
(0,16 ns/pF) C
L
923 ns
+
(0,55 ns/pF) C
L
339 ns
+
(0,23 ns/pF) C
L
212 ns
+
(0,16 ns/pF) C
L
13 ns
+
(0,55 ns/pF) C
L
4 ns
+
(0,23 ns/pF) C
L
2 ns
+
(0,16 ns/pF) C
L
13 ns
+
(0,55 ns/pF) C
L
4 ns
+
(0,23 ns/pF) C
L
2 ns
+
(0,16 ns/pF) C
L
93 ns
+
(0,55 ns/pF) C
L
44 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
63 ns
+
(0,55 ns/pF) C
L
24 ns
+
(0,23 ns/pF) C
L
17 ns
+
(0,16 ns/pF) C
L
33 ns
+
(0,55 ns/pF) C
L
19 ns
+
(0,23 ns/pF) C
L
12 ns
+
(0,16 ns/pF) C
L
SYMBOL
MIN.
TYP.
MAX.
TYPICAL
EXTRAPOLATION
FORMULA
January 1995
5
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