73S8010C
Smart Card Interface
DATA SHEET
SEPTEMBER 2005
DESCRIPTION
The TERIDIAN 73S8010C is a single smart card interface
IC. It provides full electrical compliance with ISO-7816-3,
EMV 4.0 specifications.
Interfacing with the host is done through the two-wire I
2
C
bus. Data exchange with the card is managed from the
system controller using the I/O line (and eventually the
auxiliary I/O lines).
An on-chip oscillator using an external crystal, or
connection to a clock signal coming from the system
controller can generate the card clock signal.
The TERIDIAN 73S8010C IC incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
DC-DC converter.
With its high-efficiency DC-DC converter, the TERIDIAN
73S8010C is a cost-effective solution for any smart card
reader application to be powered up from a single 2.7V to
3.6V power supply.
Hardware support for auxiliary I/O lines, C4 / C8 contacts,
is provided.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the protection
circuitry. The fault can be a card over-current, a V
DD
(digital power supply), a V
CC
(card power supply) or an
over-heating fault.
FEATURES
•
Card Interface:
Complies with ISO-7816-3, EMV 4.0
A DC-DC Converter provides 3V / 5V to the card
from an external power supply input
High-efficiency converter: > 80% @ V
PC
=3.3V,
V
CC
=5V and I
CC
= 65mA
Up to 100mA supplied current to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on card
removal or fault detected by the protection circuitry
Protection include 2 voltage supervisors that detect
voltage drops on V
CC
card and V
DD
power supplies
The V
DD
voltage supervisor threshold value can be
externally adjusted
True over-current detection 150mA
1 card detection input
Auxiliary I/O lines, for C4 / C8 contact signals
Host Interface:
Fast mode, 400kbps I
2
C slave bus
8 possible devices in parallel
One control register and one status register
Interrupt output to the host for fault detection
Crystal oscillator or host clock, up to 27MHz
Power Supply:
V
PC
: 2.7V to 3.6V
V
DD
: 2.7V to 3.6V
6kV ESD Protection on the card interface
Package: SO28 or 32QFN
•
•
•
•
ADVANTAGES
•
•
Single smart card interface
The inductor-based DC-DC converter provides higher
current and efficiency than usual charge-pump
capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and SAMs:
(100mA max)
Power down mode: 2
µ
A typical
Small Format (5x5mm) 32QFN package option
APPLICATIONS
•
•
•
Set-Top-Boxes, DVD / HDD Recorders:
Conditional Access and Pay-per-View slots
Point of Sales & Transaction Terminals
EMV slots in cell phones and PDAs
•
•
Page: 1 of 27
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
73S8010C
Smart Card Interface
DATA SHEET
FUNCTIONAL DIAGRAM
VDD
[20]
21
VDDF_ADJ
[17]
18
VPC
[3]
6
[4, 6, 8, 16, 25, 32]
7, 9
NC
[2]
5
[21]
22
GND
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
VDD FAULT
VCC FAULT
LIN
GND
GND
PWRDN
SCL
[5]
8
[18]
19
DC-DC
CONVERTER
&
VOLTAGE
SUPERVISOR
[1]
4
[12]
14
Int_Clk
SDA
[19]
20
R-C
OSC.
[15]
17
VCC
SAD0
SAD1
SAD2
INT
[29]
1
[30]
2
[31]
3
I
2
C
DIGITAL
&
FAULT LOGIC
ICC RESET
BUFFER
[14]
16
RST
[22]
23
ISO-7816
SEQUENCER
ICC CLOCK
BUFFER
[13]
15
CLK
[7]
10
XTALIN
[23]
24
PRES
XTAL
OSC
[24]
25
XTALOUT
CLOCK
GENERATION
OVER
TEMP
TEMP FAULT
[26]
26
[9]
11
IOUC
[27]
27
I/O
AUX1UC
AUX2UC
[28]
28
ICC I/O BUFFERS
[11]
13
[10]
12
AUX1
AUX2
Pin number reference to SO28 Package
[Pin number]
reference to 32QFN Package
Figure 1: 73S8010C Block Diagram
Page: 2 of 27
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
73S8010C
Smart Card Interface
DATA SHEET
PIN DESCRIPTION
CARD INTERFACE
NAME
I/O
AUX1
AUX2
RST
CLK
PRES
VCC
GND
PIN
(SO)
11
13
12
16
15
10
17
14
PIN
(QFN)
9
11
10
14
13
7
15
12
DESCRIPTION
Card I/O: Data signal to/from card. Includes a pull-up resistor to V
CC.
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V
CC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V
CC.
Card reset: provides reset (RST) signal to card.
Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by the crystal
oscillator frequency and CLKSEL bits in the control register.
Card Presence switch: active high indicates card is present. Includes a pull-down resistor.
Card power supply – logically controlled by sequencer, output of DC-DC converter. Requires an
external filter capacitor to the card GND.
Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
NAME
XTALIN
XTALOUT
VDDF_ADJ
NC
PIN
(SO)
PIN
(QFN)
DESCRIPTION
Crystal oscillator input: can either be connected to crystal or driven as a source for card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock
input.
V
DD
threshold adjustment input: this pin can be used to overwrite higher V
DDF
value (that controls
deactivation of the card). Must be left open if unused.
Non-connected pin.
24
25
18
7, 9
23
24
17
4, 6,
8, 16,
25, 32
POWER SUPPLY AND GROUND
NAME
VDD
VPC
GND
GND
GND
LIN
PIN
(SO)
21
6
4
14
22
5
PIN
(QFN)
20
3
1
12
21
2
DESCRIPTION
System controller interface supply voltage, and supply voltage for internal circuitry.
DC-DC converter power supply source.
DC-DC converter ground.
Smart Card I/O ground.
Digital ground.
External inductor. Connect external inductor from pin 5 to VPC. Keep the inductor close to pin 5.
Page: 3 of 27
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
73S8010C
Smart Card Interface
DATA SHEET
MICROCONTROLLER INTERFACE
PIN
(SO)
23
8
PIN
(QFN)
22
5
NAME
INT
PWRDN
DESCRIPTION
Interrupt output (negative assertion). Interrupt output signal to the processor. A 20kΩ pull up to V
DD
is provided internally.
Power Down control input. Active High. When Power Down (PD) mode is activated, all internal
analog functions are disabled to place the 73S8010C in its lowest power consumption mode. Must
be tied to ground when power down function is not used.
Serial device address bits. Digital inputs for address selection that allows the connection of up to 8
devices in parallel. Address selections as follows:
SAD2
0
0
0
0
1
1
1
1
SAD1
0
0
1
1
0
0
1
1
SAD0
0
1
0
1
0
1
0
1
I C Address (7 bits)
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
2
SAD0
SAD1
SAD2
1
2
3
29
30
31
SCL
SDA
I/OUC
AUX1UC
AUX2UC
19
20
26
27
28
18
19
26
27
28
Note: Pins SADO and SAD1 are internally pulled-down and SAD2 is internally pulled-up.
The default address when left unconnected is 48h.
2
I C clock signal input.
I C bi-directional serial data signal.
System controller data I/O to/from the card. Includes internal pull-up resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to V
DD.
2
Page: 4 of 27
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
73S8010C
Smart Card Interface
DATA SHEET
HOST INTERFACE (I
2
C BUS)
A fast-mode 400kHz I
2
C bus slave interface is used for controlling the device and reading the status of the device
via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SADO, SAD1, and SAD2. This
allows up to 8 devices to be connected in parallel.
Device Address Selections
SAD2
0
0
0
0
1
1
1
1
SAD1
0
0
1
1
0
0
1
1
2
SAD0
0
1
0
1
0
1
0
1
I
2
C Address
(7 bits)
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
Note: bit 0 of the I C address is the R/W bit. Refer to figures 2 and 3 for usage.
CONTROL register
Power On Reset = 00h
Name
Bit
Description
When set, initiates an activation and a cold reset procedure; when reset,
Start/Stop
0
initiates a deactivation sequence
When set, initiates a warm reset procedure; automatically reset by hardware
Warm reset
1
when the card starts answering or when the card is declared mute
5v and 3v
2
When set, V
CC
= 3v; when reset, V
CC
= 5v
Clock Stop
3
When set, card clock is stopped. Bit 4 determines the card clock stop level
Clock Stop Level
4
When set, card clock stops high; when reset card clock stops low
Bits 5 and 6 determine the clock rate to the card. See card clock rate selection
Clksel1
5
table for more details.
Clksel2
6
When set, data is transferred between I/O (AUX1, AUX2) and I/OUC
I/O enable
7
(AUX1UC, AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC) are high impedance.
Card clock rate selection table
Bit Clksel2
0
0
1
1
Bit Clksel1
0
1
0
1
Card Clock
Clkin/8
Clkin/4
Clkin/2
Clkin (Xtalin)
Page: 5 of 27
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
电机控制
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