INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT03
Quad 2-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES
•
Level shift capability
•
Output capability: standard (open drain)
•
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT03
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to V
CC
. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and V
Omax
.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
TYPICAL
SYMBOL
t
PZL
/ t
PLZ
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) +
∑
(V
O2
/R
L
)
×
duty factor LOW, where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
V
O
= output voltage in V
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
R
L
= pull-up resistor in MΩ
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
∑
(V
O2
/R
L
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
3. The given value of C
PD
is obtained with:
C
L
= 0 pF and R
L
=
∞
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per gate
notes 1, 2 and 3
CONDITIONS
HC
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
8
3.5
4.0
HCT
10
3.5
4.0
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
NAME AND FUNCTION
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
74HC/HCT03
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
nA
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
nB
L
H
L
H
OUTPUT
nY
Z
Z
Z
L
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
V
CC
V
O
I
IK
−I
OK
−I
O
±I
CC
;
±I
GND
T
stg
P
tot
PARAMETER
DC supply voltage
DC output voltage
DC input diode current
DC output diode current
DC output sink current
DC VCC or GND current
storage temperature range
power dissipation per package
plastic DIL
plastic mini-pack (SO)
750
500
mW
mW
−65
MIN.
−0.5
−0.5
MAX.
+7
+7
20
20
25
50
+150
UNIT
V
V
mA
mA
mA
mA
°C
CONDITIONS
74HC/HCT03
for V
I
< −0.5
V or V
I
>
V
CC
+ 0.5 V
for V
O
< −0.5
V
for
−
0.5 V
<
V
O
for temperature range;
−40
to +125
°C
74HC/HCT
above +70
°C:
derate linearly with 12 mW/K
above +70
°C:
derate linearly with 8 mW/K
December 1990
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
DC CHARACTERISTICS FOR 74HC
74HC/HCT03
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”,
except that the V
OH
values are
not valid for open drain. They are replaced by I
OZ
as given below.
Output capability: standard (open drain), excepting V
OH
I
CC
category: SSI
Voltages are referenced to GND (ground = 0 V)
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min. typ.
I
OZ
HIGH level output
leakage current
−40
to +85
−40
to +125
UNIT
V
CC
(V)
2.0
to
6.0
V
I
OTHER
TEST CONDITIONS
max. min. max. min. max.
0.5
5.0
10.0
µA
V
IL
V
O
= V
O(max)(1)
or GND
Note
1. The maximum operating output voltage (V
O(max)
) is 6.0 V.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min. typ.
t
PZL
/
t
PLZ
t
THL
propagation delay
nA, nB to nY
output transition time
28
10
8
19
7
6
max.
95
19
16
75
15
13
−40
to +85
min. max.
120
24
20
95
19
16
−40
to
+125
min.
max.
145
29
25
110
22
19
ns
ns
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
UNIT
V
CC
WAVEFORMS
(V)
TEST CONDITIONS
Fig.6
December 1990
5
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