INTEGRATED CIRCUITS
74F524
8-bit register comparator (open-collector
+ 3-State)
Product specification
IC15 Data Handbook
1990 Aug 07
Philips
Semiconductors
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
FEATURES
•
8-Bit bidirectional register with bus-oriented input-output
•
Independent serial input-output to register
•
Register bus comparator with ‘equal to’, ‘greater than’ and
‘less than’ outputs
PIN CONFIGURATION
S0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
1
2
3
4
5
6
7
8
9
10
20 V
CC
19 S1
18 SE
17 C/SI
16 C/SO
15 EQ
14 GT
13 LT
12 M
11 CP
•
Cascadable in groups of 8-bits
•
Open collector comparator outputs for AND-wired expansion
•
Two’s complement or magnitude compare
DESCRIPTION
The 74F524 is an 8-bit bidirectional register with parallel input and
output, plus serial input and output progressing from MSB to LSB.
All data inputs, serial and parallel, are loaded by the rising edge of
the clock. The device functions are controlled by two control lines
(S0, S1) to execute shift, load, hold and read out. An 8-bit
comparator examines the data stored in the registers and on the
data bus. Three true-High, open collector outputs representing
‘register equal to bus’, ‘register greater than bus’ and ‘register less
than bus’ are provided. These outputs can be disabled to the OFF
state by the use of Status Enable (SE). A mode control has also
been provided to allow Two’s Complement as well as magnitude
compare. Linking inputs are provided for expansion to longer words.
I/O7
GND
SF00970
TYPE
74F524
TYPICAL f
MAX
65MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
110mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F524N
N74F524D
PKG DWG #
20-pin plastic DIP
20-pin plastic SOL
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
I/On
S0, S1
C/SI
CP
SE
M
I/On
C/SO
LT
EQ
Parallel data inputs
Mode select inputs
Status priority or serial data input
Clock pulse input (active rising edge)
Status enable input (active Low)
Compare mode select input
3-state parallel data outputs
Status priority or serial data output
Register less than bus output
Register equal to bus output
DESCRIPTION
74F(U.L.)
HIGH/LOW
3.5/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
50/33
OC/33
OC/33
OC/33
LOAD VALUE
HIGH/LOW
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
1.0mA/20mA
OC/20mA
OC/20mA
OC/20mA
GT
Register greater than bus output
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
OC=Open Collector
1990 Aug 07
2
853–0373 00135
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC SYMBOL for 74F456
12
18
SELECT FUNCTION TABLE
S0
L
S1
L
H
L
OPERATION
HOLD–Retains data in shift register
READ–Read contents in register onto data bus
SHIFT–Allows serial shifting on next rising clock
edge
M
17
1
19
11
C/SI
S0
S1
CP
SE
C/SO
LT
GT
EQ
16
13
14
15
L
H
H
H
LOAD–Load data on bus into register
H = High voltage level
L = Low voltage level
One port of an 8-bit comparator is attached to the data bus while the
other port is tied to the outputs of the internal register. Three
active-OFF Open Collector outputs indicate whether the contents
held in the shift register are ‘greater than’ (GT). ‘less than’ (LT), or
‘equal to’ (EQ) the data on the input bus. A High signal on the Status
Enable (SE) input disables these outputs to the OFF state. A mode
control (M) input allows selection between a straightforward
magnitude compare or a comparison between Two’s complement
numbers.
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
2
V
CC
= Pin 20
GND = Pin 10
3
4
5
6
7
8
9
SF00971
LOGIC SYMBOL (IEEE/IEC) for 74F456
COMP
1
19
11
12
17
18
2
3
4
5
6
7
8
9
0
1
M
C4/2/4
M5 MAGNITUDE
2D
M6 TWO’s COMPLEMENT
&
G7
13
14
15
16
0
3
0=HOLD
1=READ
2=SHIFT
3=LOAD
NUMBER REPRESENTATION SELECT TABLE
M
L
Magnitude compare
OPERATION
H
Two’s Complement compare
H = High voltage level
L = Low voltage level
For ‘greater than’ or ‘less than’ detection, the C/SI input must be
held High, as indicated in the Function Table. The internal logic is
arranged such that a Low signal on the C/SI input places the
‘greater than’ and ‘less than’ outputs in their off state. (Note that this
off state serves also as the active state when C/SI is High. It is
intended for use in expansion to word lengths greater than 8 bits
using multiple 74S524s as explained in the next 3 paragraphs.) The
C/SO output will be forced High if the ‘equal to’ status condition
exists; otherwise, C/SO will be held Low.
Word length expansion (in groups of 8 bits) can be achieved by
connecting the C/SO output of the more significant byte to the C/SI
input of the next less significant byte and also to its own SE input
(see Application Figure 1). The CS/I input of the most significant
device is held High while the SE input of the least significant device
is held Low. The corresponding status outputs are AND-wired
together. In the case of two’s complement number compare, only the
Mode input to the most significant device should be High. the Mode
inputs to all other cascaded devices are held Low.
Suppose that an inequality condition is detected in the most
significant device. Assuming that the byte stored in the register is
greater than the byte on the data bus, then the EQ and LT outputs
will be pulled Low, whereas the GT output will float High. Also, the
3, 4D
1,5,6,7>I/O
1,5,6,7<I/O
1,5,6,7=I/O
SF00972
FUNCTIONAL DESCRIPTION
The 74F524 contains eight D-type flip-flops connected as a shift
register with provision for either parallel or serial loading. Parallel
data may be read from or loaded into the registers via the data bus
I/O0–I/O7. Serial data is loaded into the register from the C/SI input
and may be shifted through the register and out through the C/SO
output. Both parallel and serial data entry occurs on the rising edge
of the clock (CP). The operation of the shift register is controlled by
two signals, S0 and S1, according to the Select Function Table. The
3-State parallel output buffers are enabled only in the READ mode.
1990 Aug 07
3
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
CS/O output of the most significant device will be forced Low,
disabling the subsequent devices but enabling its own status
outputs. The corrected status condition is thus indicated. The same
applies if the register byte is less than the data byte, only in this
case the EQ and GT outputs go Low, whereas the LT output floats
High.
If an equality condition is detected in the most significant device, its
C/SO output is forced High. This enables the next less significant
device and disables its own status outputs. In this way, the status
output proximity is handed down to the next less significant device
which now effectively becomes the most significant byte. The worst
case propagation delay for a compare operation involving ‘n’
cascaded 74F524s will be when an equality condition is detected in
all but the least significant byte. In this case, the status priority has
to ripple all the way down the chain before the correct status output
is established. Typically, this will take 35+6(n–2) ns.
APPLICATION
V
CC
GREATER THAN
EQUAL TO
LESS THAN
H = TWO’s COMPLEMENT
L = MAGNITUDE
M
H
GT
EQ
LT
SE
C/SI
C/SO
S0
S1
I/O
C/SI
S0
S1
I/O
C/SO
C/SI
S0
S1
I/O
C/SO
L
M
GT
EQ
LT
SE
M
GT
EQ
LT
SE
L
L
RD
WR
MSB
8
8
LSB
8
SF01012
Figure 1. Cascading 74F524s for Comparing Longer Words
FUNCTION TABLE
INPUTS
SE
H
H
H
H
H
H
H
L
L
L
L
L
L
(1) =
2 =
H =
L =
X =
C/SI
H
L
X
H
L
H
L
L
L
L
H
H
S0
L
L
H
L
L
H
H
H or L
2
H or L
2
H or L
2
H or L
2
H or L
2
S1
L
L
L
H
H
H
H
H or L
2
H or L
2
H or L
2
H or L
2
H or L
2
Data comparison
X
X
X
X
X
X
X
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
EQ
H
H
H
H
H
H
H
L
H
L
L
H
L
OUTPUTS
GT
H
H
H
H
H
H
H
H
H
H
H
L
L
LT
H
H
H
H
H
H
H
H
H
H
L
L
H
C/SO
(1)
L
Q0
(1)
L
(1)
L
L
L
L
L
H
L
Compare
(GT=CT=on)
Compare
(GT=CT=off)
Load
Shift
Read
OPERATING MODE
Hold
H
H or L
2
H or L
2
OA–OH < I/O0–I/O7
High if I/On=Dn, otherwise Low
Must meet setup and hold time requirements
High voltage level
Low voltage level
Don’t care
1990 Aug 07
4
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC DIAGRAM
S0
1
S1 19
SE 18
17
C/SI
16
C/SO
15
CP Q
I/O0
2
D
Q
EQ
CP Q
I/O1
3
D
Q
CP Q
I/O2
4
D
Q
14
GT
CP Q
I/O3
5
D
Q
CP Q
I/O4
6
D
Q
CP Q
I/O5
7
D
Q
CP Q
I/O6
8
D
Q
13
LT
I/O7
9
CP Q
D
Q
CP 11
12
M
V
CC
= Pin 20
GND = Pin 10
SF00973
1990 Aug 07
5
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