ICS93V855I
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
•
•
•
•
•
•
Low skew, low jitter PLL clock driver
External feedback pins for input to output
synchronization
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 170 MHz
Operating Temperature –45°C to +85°C
•
•
•
CYCLE - CYCLE jitter:<75ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
Block Diagram
Functionality
INPUTS
AVDD CLK_INT CLK_INC
GND
GND
FB_OUTT
FB_OUTC
DDRT0
DDRC0
DDRT1
DDRC1
OUTPUTS
DDRT
L
H
L
H
Hi-Z
DDRC FB_OUTT FB_OUTC
H
L
H
L
Hi-Z
L
H
L
H
Hi-Z
H
L
H
L
Hi-Z
H
L
H
L
PLL State
Bypassed/Off
Bypassed/Off
On
On
Off
L
H
L
H
2.5V
(nom)
2.5V
(nom)
2.5V
<20 MHz <20 MHz
(nom)
Control
Logic
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
AVDD2.5
0783C—06/01/04
ICS93V855I
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
DDRC0
DDRT0
VDD2.5
CLK_INT
CLK_INC
AVDD2.5
AGND
GND
DDRC1
DDRT1
VDD2.5
DDRT2
DDRC2
GND
DDRC3
DDRT3
VDD2.5
GND
FB_INC
PWR
OUT
OUT
PWR
IN
IN
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
IN
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" reference clock input.
"Complimentary" reference clock input.
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
Ground pin.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase error.
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Power supply, nominal 2.5V
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output must
be connect to FB_INT.
Complement single-ended feedback output, dedicated external feedback.
It switches at the same frequency as other DDR outputs, This output must
be connect to FB_INC.
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
21
22
23
FB_INT
VDD2.5
FB_OUTT
IN
PWR
OUT
24
25
26
27
28
FB_OUTC
GND
VDD2.5
DDRT4
DDRC4
OUT
PWR
PWR
OUT
OUT
0783C—06/01/04
2
ICS93V855I
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V
(VDDI) . . . . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs: VI . . . . . . . . . . . . . . . . . . . . . . . V
SS
–0.5 V to V
DD
+0.5 V
Logic Outputs: VO . . . . . . . . . . . . . . . . . . . . . V
SS
–0.5 V to V
DD
+0.5 V
Input clamp current: IIK (VI < 0 or VI > VDD) +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD)
+/- 50mA
Continuous output current: IO (VO = 0 to VDD) +/- 50mA
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
MIN
TYP
PARAMETER
CONDITIONS
V
I
= V
DD
or GND
I
IH
5
Input High Current
I
IL
V
I
= V
DD
or GND
Input Low Current
C
L
= 0pf, R
L
= 120 ohms
Operating Supply
I
DD2.5
Current
C
L
= 0pf, R
L
= 120 ohms
I
DDPD
V
DD
= 2.3V, V
OUT
= 1V
Output High Current
I
OH
-18
Output Low Current
High Impedance
Output Current
Input Clamp Voltage
I
OL
I
OZ
V
IK
V
OH
V
DD
= 2.3V, V
OUT
= 1.2V
V
DD
=2.7V, Vout=V
DD
or GND
Iin = -18mA
V
DD
= min to max,
I
OH
= -1 mA
V
DD
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DD
= 2.3V
I
OH
=12 mA
VI = V
DD
or GND
VI = V
DD
or GND
26
±10
-1.2
V
DD
- 0.1
1.7
0.1
0.6
3
3
V
pF
pF
MAX
5
250
100
UNITS
µA
µA
mA
µA
mA
mA
μA
V
V
V
High-level output voltage
Low-level output voltage
V
OL
C
IN
Input Capacitance
1
C
OUT
Output Capacitance
1
1
Guaranteed by design and characterization, not 100% tested in production.
0783C—06/01/04
3
ICS93V855I
DC Electrical Characteristics
T
A
= -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage (note
2)
Differential input signal
voltage (note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
Operating free-air
temperature
SYMBOL
V
DD Q
, A
VDD
V
IL
V
IH
V
IN
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
CONDITIONS
CLK_INT, CLK_INC, FB_INC,
FB_INT
CLK_INT, CLK_INC, FB_INC,
FB_INT
MIN
2.3
TYP
2.5
0.4
V
DD
/2 + 0.18
-0.3
0.36
0.7
V
D D
/2 - 0.15
V
D D
/2 - 0.2
-45
V
DD
/2
2.1
V
DD
+ 0.3
V
DD
+ 0.6
V
DD
+ 0.6
V
D D
/2 + 0.15
V
D D
/2 + 0.2
85
MAX
2.7
V
DD
/2 - 0.18
UNITS
V
V
V
V
V
V
V
V
°C
V
ID
V
OX
V
IX
T
A
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential inputs signal voltages specifies the differential voltage [VT-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VD D and is the voltage at which the
differential signal must be crossing.
0783C—06/01/04
4
ICS93V855I
Switching Characteristics
T
A
= -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
3
freq
op
33
Max clock frequency
Application Frequency
freq
App
60
3
Range
Input clock duty cycle
d
t in
40
t
sl(o )
Output clock slew rate
1
CLK stabilization
T
ST AB
Low-to high level propagation
1
CLK_IN to any output
5.5
t
PL H
delay time
High-to low level propagation
1
t
PH L
CLK_IN to any output
5.5
delay time
t
en
PD# to any output
5
Output enable time
PD# to any output
5
Output disable time
t
dis
t
jit (pe r)
Period jitter
-75
t
jit(hpe r)
Half-period jitter
-100
Over the application
1
Input clock slew rate
t
sl(I)
frequency range
t
cyc
-t
cyc
Cycle to Cycle Jitter
-75
4
t
(phase erro r)
-50
Phase error
t
skew
Output to Output Skew
40
t
r
, t
f
Rise Time, Fall Time
Load = 120φ /16pF
650
800
MAX
233
170
60
2
100
UNITS
MHz
MHz
%
v/ns
µs
ns
ns
ns
ns
ps
ps
v/ns
ps
ps
ps
ps
75
100
2
75
50
60
950
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The PLL
Locks over the Max Clock Frequency range, but the device doe not necessarily
meet other timing parameters.
4. Does not include jitter.
0783C—06/01/04
5
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