2:1 Differential-to-LVDS Multiplexer
ICS854S01I
DATASHEET
General Description
The ICS854S01I is a high performance 2:1 Differential-to-LVDS
Multiplexer. The ICS854S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS or CML levels.
The ICS854S01I is packaged in a small 3mm x 3mm 16 VFQFN
package, making it ideal for use on space constrained boards.
Features
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2:1 LVDS MUX
One LVDS output pair
Two differential clock inputs can accept: LVPECL, LVDS, CML
Maximum input/output frequency: 2.5GHz
Translates LVCMOS/LVTTL input signals to LVDS levels by using
a resistor bias network on nPCLK0, nPCLK1
RMS additive phase jitter: 0.06ps (typical)
Propagation delay: 600ps (maximum)
Part-to-part skew: 350ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
0
Q
nQ
1
Pin Assignment
GND
GND
PCLK0 1
nPCLK0
2
16 15 14 13
12 GND
11 Q
10 nQ
9 GND
5
RESERVED
PCLK1 3
CLK_SEL
Pulldown
nPCLK1 4
6
CLK_SEL
7
nc
ICS854S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
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©2017 Integrated Device Technology, Inc.
V
DD
V
DD
nc
8
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 16
8, 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
RESERVED
CLK_SEL
nc
V
DD
GND
nQ, Q
Input
Input
Input
Input
Reserve
Input
Unused
Power
Power
Output
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Reserve pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
No connects.
Power supply pins.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
37
37
Maximum
Units
pF
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
0
1
PCLK Selected
PCLK0, nPCLK0
PCLK1, nPCLK1
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ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
40
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-10
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
μA
μA
Table 4C. LVPECL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High
Current
Input Low
Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.15
1.2
1.2
V
DD
Minimum
Typical
Maximum
150
Units
μA
μA
μA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
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ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tjit
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Part-to-Part Skew;
NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation;
NOTE 4
f
OUT
= 155.52MHz, V
PP
=
400mV
20% to 80%
100
49
86
155.52MHz, Integration Range:
12kHz – 20MHz)
250
400
0.06
350
275
51
Test Conditions
Minimum
Typical
Maximum
2.5
600
Units
GHz
ps
ps
ps
ps
%
dB
tsk(pp)
t
R
/ t
F
odc
MUX_
ISOLATION
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters measured at
1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ outputs measured differentially. See Parameter Measurement Information to MUX Isolation diagram.
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ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.06ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”
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©2017 Integrated Device Technology, Inc.
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