with Peak EMI reduction. PCS3P624Z05 is an eight-pin
version, accepts one reference input and drives out five
low-skew Timing-Safe™ clocks. PCS3P624Z09 accepts
one reference input and drives out nine low-skew Timing-
Safe™clocks.
PCS3P624Z05/09 has a DLY_CTRL for adjusting the
Input-Output clock delay, depending upon the value of
capacitor connected at this pin to GND.
PCS3P624Z05/09 operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
Application
PCS3P624Z05/09 is targeted for use in Displays and
Functional Description
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute high frequency Timing-Safe™ clocks
memory interface systems.
General Block Diagram
PLL
CLKIN
DLY_CTRL
CLKOUT1
CLKOUT2
CLKOUT3
PLL
CLKIN
MUX
DLY_CTRL
CLKOUTA1
CLKOUTA2
CLKOUTA3
PCS3P624Z05B/C
CLKOUTA4
CLKOUT4
S2
S1
Select Input
Decoding
CLKOUTB1
CLKOUTB2
CLKOUTB3
PCS3P624Z09B/C
CLKOUTB4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2008
rev 0.1
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
PCS3P624Z05B/C
PCS3P624Z09B/C
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS3P624Z05/09
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below
the
reference
frequency
with
a
specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the DLY_CTRL pin
is the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including DLY_CTRL, must be equally loaded.
Even if DLY_CTRL is not used, it must have a capacitive
load equal to that on other outputs, for obtaining zero-
input-output delay.
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
High Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 15
May 2008
rev 0.1
Pin Configuration for PCS3P624Z05B/C
PCS3P624Z05B/C
PCS3P624Z09B/C
CLKIN
1
CLKOUT1
2
PCS3P624Z05B/C
CLKOUT2
3
GND
4
8
DLY_CTRL
CLKOUT4
VDD
CLKOUT3
7
6
5
Pin Description for PCS3P624Z05B/C
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN
1
Type
I
O
O
P
O
P
O
O
Buffered clock output
4
Buffered clock output
4
Ground
Buffered clock output
4
3.3V supply
Buffered clock output
4
Description
External reference Clock input, 5V tolerant input
CLKOUT1
2
CLKOUT2
2
GND
CLKOUT3
2
VDD
CLKOUT4
2
DLY_CTRL
External Input-Output Delay control
. This pin can be used as clock output
4
High Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 15
May 2008
rev 0.1
Pin Configuration for PCS3P624Z09B/C
PCS3P624Z05B/C
PCS3P624Z09B/C
CLKIN
1
CLKOUTA1
2
CLKOUTA2
3
VDD
4
GND
PCS3P624Z09B/C
5
16
15
14
13
12
11
10
9
DLY_CTRL
CLKOUTA4
CLKOUTA3
VDD
GND
CLKOUTB4
CLKOUTB3
S1
CLKOUTB1
6
CLKOUTB2
7
S2
8
Pin Description for PCS3P624Z09B/C
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
1
Pin Type
I
O
O
P
P
O
O
I
I
O
O
P
P
O
O
O
Buffered clock Bank A output
4
Buffered clock Bank A output
4
3.3V supply
Ground
Buffered clock Bank B output
4
Buffered clock Bank B output
4
Description
External reference Clock input, 5V tolerant input
CLKOUTA1
2
CLKOUTA2
2
VDD
GND
CLKOUTB1
2
CLKOUTB2
2
S2
3
S1
3
CLKOUTB3
2
CLKOUTB4
2
GND
VDD
CLKOUTA3
2
CLKOUTA4
2
DLY_CTRL
2
Select input, bit 2.See
Select Input Decoding table for PCS3P624Z09
for more details
Select input, bit 1.See
Select Input Decoding table for PCS3P624Z09
for more details
Buffered clock Bank B output
4
Buffered clock Bank B output
4
Ground
3.3V supply
Buffered clock Bank A output
4
Buffered clock Bank A output
4
External Input-Output Delay control
. This pin can be used as clock output
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
High Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 15
May 2008
rev 0.1
Select Input Decoding table for PCS3P624Z09
PCS3P624Z05B/C
PCS3P624Z09B/C
S2
0
0
1
1
S1
0
1
0
1
CLKOUT A1 - A4 CLKOUT B1 - B4 DLY_CTRL
1
Output Source
Three-state
Driven
Driven
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
Driven
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
Notes: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and
the Output.
Spread Spectrum Control and Input-Output Skew Table
Frequency (MHz)
75
Device
PCS3P624Z05B / 09B
PCS3P624Z05C / 09C
Deviation (
±%)
0.25
0.5
Input-Output Skew (±T
SKEW
)
0.0625
0.125
Note: T
SKEW
is measured in units of the Clock Period
Absolute Maximum Ratings
Symbol
VDD
VIN
T
STG
T
s
T
J
T
DV
DC Input Voltage (CLKIN)
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Supply Voltage to Ground Potential
Rating
-0.5 to +4.6
-0.5 to +7
-65 to +125
260
150
2
Unit
V
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
-40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
High Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
