ADVANCE
‡
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
18Mb SYNCBURST
™
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V ±0.165V or +2.5V ±0.125V power supply
(V
DD
)
• Separate +3.3V or +2.5V isolated output buffer supply
(V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
®
BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data I/Os,
and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L1MY18P, MT58V1MV18P,
MT58L512Y32P, MT58V512V32P,
MT58L512Y36P, MT58V512V36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V
I/O, Pipelined, Single-Cycle Deselect
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
2.5V V
DD
, 2.5V I/O
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
3.3V V
DD
, 3.3V or 2.5V I/O
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP (3-chip enable)
165-pin FBGA
119-pin BGA
• Operating Temperature Range
Commercial (0ºC to +70ºC)
MARKING
-6
-7.5
-10
-7.5
-10
119-Pin BGA
2
MT58L1MY18P
MT58L512Y32P
MT58L512Y36P
MT58V1MV18P
MT58V512V32P
MT58V512V36P
T
F*
B
None
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
Part Number Example:
MT58L1MY18PT-6
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01
1
©2000, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
‡
PRODUCTS
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
20
SA0, SA1, SAs
MODE
ADDRESS
REGISTER
20
18
20
2
SA0-SA1
SA1'
ADV#
CLK
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BWb#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
1 Meg x 9 x 2
MEMORY
ARRAY
9
18
SENSE
AMPS
18
OUTPUT
REGISTERS
18
OUTPUT
BUFFERS
E
18
BWa#
BWE#
GW#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
DQs
DQPa
DQPb
CE#
CE2
CE2#
OE#
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
19
SA0, SA1, SAs
ADDRESS
REGISTER
19
17
SA0-SA1
19
MODE
ADV#
CLK
Q1
SA1'
BINARY
COUNTER
SA0'
CLR
Q0
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
9
BYTE
“d”
WRITE DRIVER
BYTE
“c”
WRITE DRIVER
BYTE
“b”
WRITE DRIVER
BYTE
“a”
WRITE DRIVER
9
BWc#
9
9
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
36
SENSE
AMPS
36
OUTPUT
REGISTERS
36
BWb#
BYTE “b”
WRITE REGISTER
9
9
MEMORY
ARRAY
OUTPUT
BUFFERS
E
36
DQs
DQPa
DQPb
DQPc
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
9
ENABLE
REGISTER
36
PIPELINED
ENABLE
4
INPUT
REGISTERS
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for
detailed information.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION
The Micron
®
SyncBurst
™
SRAM family employs high-
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process.
Micron’s 18Mb SyncBurst SRAMs integrate a
1 Meg x 18, 512K x 32, or 512K x 36 SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through reg-
isters controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#), and global write (GW#).
Asynchronous inputs include the output enable (OE#),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved
and linear burst modes. The data-out (Q), enabled by
OE#, is also asynchronous. WRITE cycles can be from
one to two bytes wide (x18) or from one to four bytes wide
(x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa pins and DQPa; BWb# con-
trols DQb pins and DQPb; BWc# controls DQc pins and
DQPc; BWd# controls DQd pins and DQPd. GW# LOW
causes all bytes to be written. Parity bits are only avail-
able on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
t
KQHZ nanoseconds after the rising edge of
clock.
The device is ideally suited for Pentium and PowerPC
pipelined systems and systems that benefit from a very
wide, high-speed data bus. The device is also ideal in
generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applica-
tions.
Please refer to Micron’s Web site (www.micron.com/
sram)
for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x32
x36
NF
DQPc
1
DQc DQc
DQc DQc
V
DD
Q
V
SS
NC
DQc DQc
NC
DQc DQc
DQb DQc DQc
DQb DQc DQc
V
SS
V
DD
Q
DQb DQc DQc
DQb DQc DQc
NC
V
DD
NC
V
SS
DQb DQd DQd
DQb DQd DQd
V
DD
Q
V
SS
DQb DQd DQd
DQb DQd DQd
DQPb DQd DQd
NC
DQd DQd
x18
NC
NC
NC
PIN # x18
x32
x36
26
V
SS
27
V
DD
Q
28
NC
DQd DQd
29
NC
DQd DQd
30
NC
NF
DQPd
1
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
SS
41
V
DD
42
SA
43
SA
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x32
x36
NF
DQPa
1
DQa DQa
DQa DQa
V
DD
Q
V
SS
NC
DQa DQa
NC
DQa DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
NC
V
SS
DQa DQb DQb
DQa DQb DQb
V
DD
Q
V
SS
DQa DQb DQb
DQa DQb DQb
DQPa DQb DQb
NC
DQb DQb
x18
NC
NC
NC
PIN # x18
x32
x36
76
V
SS
77
V
DD
Q
78
NC
DQb DQb
79
NC
DQb DQb
80
SA
NF
DQPb
1
81
SA
82
SA
83
ADV#
84
ADSP#
85
ADSC#
86
OE# (G#)
87
BWE#
88
GW#
89
CLK
90
V
SS
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC BWc# BWc#
96
NC BWd# BWd#
97
CE2
98
CE#
99
SA
100
SA
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP, 3-CHIP ENABLE
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa
1
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L1MY18P_C.p65 – Rev. C; Pub. 9/01
NF/DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
1
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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