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MT18VDDS12872HY-265: 产品描述DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,; 产品类别存储存储; 文件大小616KB，共38页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT18VDDS12872HY-265概述

DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,

MT18VDDS12872HY-265规格参数

参数名称	属性值
是否Rohs认证	符合
Reach Compliance Code	compliant
最长访问时间	0.75 ns
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
JESD-30 代码	R-PDMA-N200
内存密度	9663676416 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	72
端子数量	200
字数	134217728 words
字数代码	128000000
最高工作温度	70 °C
最低工作温度
组织	128MX72
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	DIMM
封装等效代码	DIMM200,24
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	0.6 mm
端子位置	DUAL
Base Number Matches	1

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128MB, 256MB, 512MB, 1GB (x72, ECC)

200-PIN DDR SODIMM

DDR SDRAM

SMALL-OUTLINE DIMM

Features

• 200-pin, small-outline, dual in-line memory

module (SODIMM)

• ECC, 1-bit error detection and correction

• Fast data transfer rates: PC1600, PC2100, or PC2700

• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM

components or TwinDie

DDR SDRAM components

• MT9VDDT1672H (16 Meg x 72), MT9VDDT3272H (32 Meg

x 72), MT18VDDS6472H and MT9VDDT6472H (64

Meg x 72), and MT18VDDS12872H (128 Meg x 72)

• V

= V

Q = +2.5V

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

OPTIONS

MARKING

MT9VDDT1672H –128MB, MT9VDDT3272H –256MB,

MT18VDDS6472H – 512MB, MT9VDDT6472H –

512MB, MT18VDDS12872H – 1GB (ADVANCE

‡

)

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Figure 1: 200-Pin SODIMM (MO-224)

Standard 1.5in. (38.10mm)

Low Profile 1.25in. (31.75mm)

• Operating Temperature Range

Commercial (0°C

+70°C)

None

Industrial (-40°C

+85°C)

• Package

200-pin SODIMM (standard)

200-pin SODIMM (lead-free)

• Frequency/CAS Latency

6.0ns (167 MHz) 333 MT/s CL = 2.5

-335

7.5ns (133 MHz) 266 MT/s CL = 2

-262

7.5ns (133 MHz) 266 MT/s CL = 2

-26A

7.5ns (133 MHz) 266 MT/s CL = 2.5

-265

10ns (100 MHz) 200 MT/s CL = 2

-202

• PCB

Standard 1.5in. (38.10mm)

See page 2 note

Low Profile 1.25in. (31.75mm)

NOTE:

1. CL = Device CAS (READ) Latency.

2. -335 and -262 speed grades available in single-

rank module only.

3. Consult Micron for availability; industrial tem-

perature option available in -265 speed only.

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/received

with data—i.e., source-synchronous data capture

• Differential clock inputs CK and CK#

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.625µs (MT9VDDT1672H), 7.8125µs

(MT9VDDT3272H, MT18VDDS6472H,

MT9VDDT6472H, and MT18VDDS12872H)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Gold edge contacts

Table 1:

Address Table

MT9VDDT1672H

4K (A0–A11)

4 (BA0, BA1)

16 Meg x 8

1K (A0–A9)

1 (S0#)

MT9VDDT3272H MT18VDDS6472H

8K (A0–A12)

4 (BA0, BA1)

32 Meg x 8

1K (A0–A9)

1 (S0#)

2 (S0#, S1#)

MT9VDDT6472H

8K (A0–A12)

4 (BA0, BA1)

64 Meg x 8

2K (A0–A9, A11)

1 (S0#)

MT18VDDS12872H

8K (A0–A12)

4 (BA0, BA1)

64 Meg x 8

2K (A0–A9, A11)

2 (S0#, S1#)

Refresh Count

Row Addressing

Device Bank Addressing

Device Configuration

Column Addressing

Module Rank Addressing

09005aef806e057b

DDS9_18C16_32_64_128X72HG_A.fm - Rev. A 7/03 EN

‡

PRODUCTS

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

MT18VDDS12872HY-265相似产品对比

	MT18VDDS12872HY-265	MT18VDDS12872HY-26A	MT18VDDS12872HY-202	MT18VDDS12872HIY-26A	MT18VDDS12872HIY-265
描述	DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,	DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,	DDR DRAM Module, 128MX72, 0.8ns, CMOS, PDMA200,	DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,	DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,
是否Rohs认证	符合	符合	符合	符合	符合
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
最长访问时间	0.75 ns	0.75 ns	0.8 ns	0.75 ns	0.75 ns
最大时钟频率 (fCLK)	133 MHz	133 MHz	125 MHz	133 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PDMA-N200	R-PDMA-N200	R-PDMA-N200	R-PDMA-N200	R-PDMA-N200
内存密度	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	72	72	72	72	72
端子数量	200	200	200	200	200
字数	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words
字数代码	128000000	128000000	128000000	128000000	128000000
最高工作温度	70 °C	70 °C	70 °C	85 °C	85 °C
组织	128MX72	128MX72	128MX72	128MX72	128MX72
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIMM	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM200,24	DIMM200,24	DIMM200,24	DIMM200,24	DIMM200,24
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.6 mm	0.6 mm	0.6 mm	0.6 mm	0.6 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL
Base Number Matches	1	1	1	1	1

MT18VDDS12872HY-265

MT18VDDS12872HY-265概述

MT18VDDS12872HY-265规格参数

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MT18VDDS12872HY-265相似产品对比

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