Preliminary
1/2 1/3 1/4 Duty LCD Driver
!
GENERAL DESCRIPTION
NJU6543
is a 1/2 or 1/3,1/4 duty segment type LCD driver.
It incorporates 4 common driver circuits and 128 segment
driver circuits.
NJU6543
can drive maximum 256
segments in 1/2 duty ratio and maximum 384 segments in
1/3 duty ratio and maximum 512 segments in 1/4 duty
ratio.
In addition
, the
NJU6543's
useful functions meet a wide
NJU6543
!
PACKAGE OUTLINE
range of applications.
NJU6543
!
FEATURES
#
LCD driving circuit
:Max. 128outputs (4 outputs as for general purpose ports)
#
Programmable Duty Ratio
1/2 Duty Ratio
:Driving max. 256 segments
1/3 Duty Ratio
:Driving max. 384 segments
1/4 Duty Ratio
:Driving max. 512 segments
#
Programmable Bias Ratio
:1/2, 1/3 bias ratio
#
Electrical Variable Resistance :8-steps
#
Serial Data Transfer
:Shift clock max. 2MHz
#
Built-in Oscillator
:
CR oscillation with external resistor and capacitance, or external oscillation
signal input
#
Operating Voltage
#
C-MOS Technology
#
Package Outline
:3.0V / 5.0V
:
P-Sub
:LQFP144 20mm*20mm t=1.7mm(max) Pin-pitch=0.5mm
!
BLOCK DIAGRAM
COM1
V
DD
V
0
COM4 SEG1
SEG8
SEG9
SEG16 SEG17
SEG24
SEG121
SEG125/P1
SEG128/P4
EVR
V
1
V
2
V
3
V
SS
TEST
OSC
COM
Drivers
//
Segment Drivers /General Purpose Output Ports
//
Data Latch Circuit
Oscillator
Display Data Register
CSb
SCK
SI
RSTb
Decoder
Command Register
Power ON Reset Circuit
Ver.2008-11-28
-1-
NJU6543
!
PIN CONFIGURATION
•
LQFP144
SEG104
Preliminary
102
101
108
106
105
107
103
100
99
98
97
96
104
94
93
92
85
84
91
90
89
88
87
86
83
82
81
80
79
78
77
76
75
74
95
73
72
71
70
69
68
67
65
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
SEG32 36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
SEG105
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
NJU6543
SEG124
SEG125/P1
SEG126/P2
SEG127/P3
SEG128/P4
V
0
V
1
V
2
V
3
V
SS
OSC
TEST
RSTb
CSb
SI
SCK
V
DD
24
25
33
17
18
19
20
21
SEG4 8
SEG5 9
SEG6 10
SEG7 11
SEG8 12
SEG9 13
SEG10 14
15
16
22
23
26
27
28
29
30
31
32
SEG33
34
35
1
2
3
4
SEG1 5
COM1
COM2
COM3
COM4
SEG2 6
SEG3 7
-2-
Ver.2008-11-28
SEG69
Preliminary
!
TERMINAL DISCRIPTION
No.
144
133
134
135
136
137
139
Pad Name
V
DD
V
0
V
1
V
2
V
3
V
SS
TEST
Function
NJU6543
Power supply: 3V /5V
LCD driving voltage
V
0
≥
V
1
≥
V
2
≥
V
3
≥
V
SS
, V
0
≥V
DD
Bias
At 1/3 bias ratio, keep V
2
- V
3
open.
At 1/2 bias ratio, short V
2
- V
3
.
GND
V
SS
=0V
TEST
Keep TEST-V
SS
short
Reset
When RSTb is “L", command register and latch circuit is reset.
When this terminal is not used, should be V
DD
short. (keep p
ower supply
condition when hardware reset circuit is used)
Chip select
When CSb is "L", data can be read in.
Serial data input (8 bit=1word)
Serial clock
External resistor and capacitance connection terminal for CR oscillation, or
external clock input terminal
Common driver outputs
Segment driver outputs
Segment driver outputs/general purpose output ports
These 4 terminals can be used as segment outputs or general purpose
output ports by setting Command Register.
When selected as general purpose ports, data can be outputted via
these ports during COM1 timing.
According to transferred data, "H"=V
DD
or "L"=V
SS
will be outputted.
140
RSTb
141
142
143
138
1~4
5~128
CSb
SI
SCK
OSC
COM1 ~ COM4
SEG1 ~ SEG124
129~132
SEG125/P1 ~
SEG128/P4
Ver.2008-11-28
-3-
NJU6543
Preliminary
!
FUNCTION DESCRIPTION
(1) Block Function
•
Oscillator
The oscillator includes an external capacitor and an resistor.
When use external clock, input the clock signal to OSC.
•
It generates clock signal for LCD driving.
Decoder
Input serial data is decoded and sent to the appropriate block.
Command Register
Command data is written to this 8 bits command register to control
NJU6543
operation.
Display Data Register
Data is written to this 8 bits register as display data.
Latch Circuit
Data stored in display data register is assigned to the corresponding SEG/port.
Segment Driver/General Purpose Ports
Basing on display data, segment drivers output LCD SEG driving signal.
And, SEG125/P1 ~ SEG128/P4 terminals can be selected as segment driver output or general-purpose ports
by instruction.
Common Driver
Common drivers output LCD COM driving signal.
Power On Reset
When power is on,
NJU6543
is automatically initialized. And if RSTb=”L”,
NJU6543
is reset too.
Electrical Variable Resistance (E.V.R.)
The Electrical Variable Resistance adjusts LCD Driving Voltage from V1 to V3.
•
•
•
•
•
•
•
-4-
Ver.2008-11-28
Preliminary
NJU6543
During
(2) Serial Data Transfer
The transfer of
an
8-bit/word serial data is conducted by synchronizing clock via interface with CPU.
CSb=”L”, serial data is obtainable and will be read in at the rising edge of SCK signal.
After CSb becoming low, by the first word, address data is distinguished by D7 and D6.
In the case of address data(D7,D6=”0,1”), the 2nd data can be transferred continually and interrupted as
display data even if CSb maintained low. In this case, every 8-bits data will be confirmed as a word either by
th
the falling edge of the8 SCK clock or by the rising edge of the CSb clock.
After CSb becoming low, if the first word is command data(D7,D6=”1,0”or “1,1”), the after data is invalid even
though transfer can be continued without changing the polarity of CSb.( Effective the first word)
At the falling edge of CSb, SCK can be either “H” or “L”, but, at the rising edge of CSb, SCK must be low.
At this rising edge, one word is confirmed
Command data
CSb
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
Timing of Serial Data Transfer
SCK and SI (Address data and display data)
At this rising edge of CSb,
SCK=”Lo”, one word is confirmed.
when
CSb
SCK
WORD 1
WORD2
WORD n
SI
Serial Interface Format
Ver.2008-11-28
-5-
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
