NJU26904
Digital Audio Delay
■
General Description
The NJU26904 offers digital audio delay.
The NJU26904 has internal delay memory. Delay function can adjust output
time of a six-channel signal.
This delay functions are suitable for delay time adjustment such as Audio
products and time alignment such as Car Audio.
■
Package
■
FEATURES
•
6-channel Digital Audio Delay
Delay Time 84msec for monaural channel, 42msec for stereo channel at Fs=96kHz
Delay Time 169msec for monaural channel, 85msec for stereo channel at Fs=48kHz
Delay Time 254msec for monaural channel, 127msec for stereo channel at Fs=32kHz
•
Delay data width is 24 bits.
Digital Audio Format: I
2
S 24bit, Left-Justified, Right-Justified, BCK: 32/64fs
•
Adjustable Delay Time with 1sample units for 8,121 samples at maximum.
•
Selectable input sources for each channel output freely.
•
To make long delay time, the NJU26904 can be connected serially.
•
Non-Audio Format is possible.
NJU26904V-C2
- Hardware
•
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
•
Digital Audio Interface
: 3 Input ports / 3 Output ports
•
Digital Audio Format
: I
2
S 24bit, Left- Justified, Right-Justified, BCK : 32/64fs
•
Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
•
Host Interface
: I
2
C bus (Fast-mode/400kbps)
•
Power Supply
: 3.3V
•
Input terminal
: 5V Input tolerant
•
Package
: SSOP24-C2 (Pb-Free)
Ver.2008-12-02
-1-
NJU26904
■
Function Block Diagram
SCL
I C INTERFACE
SDA
HOST CONTROL
RESETb
MCK
CLKOUT
CLK
SLAVEb
Internal Pow er
(1.8V)
2
SDI0-2
SDO0-2
BCK
SERIAL AUDIO
INTERFACE
TIMING
GENERATOR /
PLL
LR
ADDRESS GENERATION UNIT
WDC
GPIO
INTERFACE
AD2
AD1
Built-in LDO
VREGO
External
Low -ESR
Capacitors
Required
Delay RAM
1.8V level terminal
Fig. 1 NJU26904 Block Diagram
-2-
Ver.2008-12-02
NJU26904
■
DSP Block Diagram
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO0_L
SDO0_R
Delay Memory
Free dividing
SDO1_L
SDO1_R
SDO2_L
SDO2_R
Fig. 2 NJU26904 Function Diagram
Ver.2008-12-02
-3-
NJU26904
■
Pin Configuration
RESETb
LR
BCK
SDI2
SDI1
SDI0
MCK
VDD
VSS
STBYb
VSS
VREGO
1
2
3
4
5
6
7
8
9
10
11
12
NJU26904
24
23
22
21
20
19
18
17
16
15
14
13
TEST
SCL
SDA
SDO2
SDO1
SDO0
WDC
AD2
AD1
SLAVEb
CLK
CLKOUT
SSOP24-C2
Fig. 3 NJU26904 Pin Configuration
■
Pin Description
Table 1 Pin Description
No. Symbol
I/O Description
No. Symbol
I/O Description
1
RESETb I
RESET (active Low)
13
CLKOUT
O
OSC Output
2
LR
I/O LR Clock
14
CLK
I
OSC Clock Input
3
BCK
I/O Bit Clock
15
SLAVEb
I
Slave select
4
SDI2
I
Audio Data Input 2 L/R
16
AD1
I
I
2
C Address 1
5
SDI1
I
Audio Data Input 1 L/R
17
AD2
I
I
2
C Address 2
6
SDI0
I
Audio Data Input 0 L/R
18
WDC
OD Clock for Watch Dog Timer
7
MCK
I/O Master Clock
19
SDO0
O
Audio Data Output 0 L/R
8
VDD
-
Power Supply +3.3V
20
SDO1
O
Audio Data Output 1 L/R
9
VSS
-
GND
21
SDO2
O
Audio Data Output 2 L/R
10
STBYb
I
For TEST (Connected to VDD)
22
SDA
OD I
2
C I/O
11
VSS
-
GND
23
SCL
I
I
2
C Clock
12
VREGO PI
Built-in Power Supply Bypass
24
TEST
I
For TEST(Connected to VSS)
* I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass
AD1 (No.16) pin and AD2 (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance. However,
these pins operate as bi-directional pins. No.11pin and No.12pin connect with V
DD
or V
SS
through 3.3kΩ resistance.
No.18pin do not connect or connect with V
DD
through 3.3kΩ resistance when unused.
VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel
between VSS (No.11) pin. A built-in power supply is used only for NJU26904 operation. Be not short-circuited of this pin.
Do not take out the current, and connect other power supplies.
-4-
Ver.2008-12-02
NJU26904
■
Absolute Maximum Ratings
( V
SS
=0V=GND, Ta=25°C )
°
Rating
Units
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage *
Supply Voltage Bypass *
In
I/O, OD
Pin Voltage *
Out
CLK
CLKOUT
Power Dissipation
Operating Voltage
Storage Temperature
V
DD
V
REGO
V
x(IN)
V
x(I/O)
,V
x(OD)
V
x(OUT)
V
x(CLK)
V
x(CLKOUT)
-0.3 to 4.2
-0.3 to 2.3
-0.3 to 5.5 (V
DD
≥
3.0V)
-0.3 to 4.2 (V
DD
< 3.0V)
-0.3 to 4.2
-0.3 to 4.2
V
V
V
565
mW
P
D
-40 to 85
T
OPR
°C
T
STR
-40 to 125
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* V
DD
: 8 pin
* V
REGO
: 12 pin
* V
x(IN)
: 1, 4, 5, 6, 10, 15, 23, 24 pin
* V
x(OD)
: 22 pin
* V
x(I/O)
: 2, 3, 7, 16, 17, 18 pin
* V
x(OUT)
: 19, 20, 21 pin
* V
x(CLK)
: 14 pin
* V
x(CLKOUT)
: 13 pin
V
DD
V
DD
(1.8V)
V
DD
V
DD
(1.8V)
■
Terminal equivalent circuit diagram
PAD
R
PD
CLK
CLKOUT
SS
Input, I/O (Input part)
(1 to 7, 22, 23pin)
(With R
PU
: 18pin With R
PD
: 15, 16, 17, 24pin)
V
V
SS
CLK/CLKOUT
(13, 14pin)
V
DD
R
PU
PAD
Output Disable
PAD
V
DD
Output, I/O (Output part)
(2, 3, 7, 16, 17, 19, 20, 21pin )
( Open Drain Output with R
PU
: 18pin)
( Open Drain Output: 22pin )
V
SS
V
SS
STBYb
(10pin)
Fig.4 NJU26904 Terminal equivalent circuit diagram
Ver.2008-12-02
-5-
MicroPython开源版块
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
