NJU26209
DAEP Decoder
General Description
The NJU26209 is a digital signal processor that provides the function of DAEP (Dolby
Automotive Entertainment Program).
A location of sound image forward is possible without a center speaker by all seats in the
car.
The applications of NJU26209 are suitable for Car Audio, Car Navigation system and other
audio products.
■
Package
Features
-Software
DAEP (Dolby Automotive Entertainment Program)
Pro Logic II
Automotive (Advanced Surround Fader, Center Image Control)
Bass Management
Time Alignment
Master Volume
Input Trim
Channel Trim
-Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency
: 12.288MHz(Standard), built-in PLL Circuit
Digital Audio Interface
: 4 Input ports / 4 Output ports
Digital Audio Format
: I
2
S 24bit, left-justified, right-justified, BCK : 32fs/64fs
Master / Slave Mode
Microcomputer Interface
I
2
C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
Operating Voltage
: V
DD
= V
DDPLL
= 1.8V
: V
DDIO
= 3.3V
Input Terminal
: +5.0V Input tolerant
Package
: SSOP44 (Pb-Free)
NJU26209V
* The detail hardware specification of the NJU26209 is described in the “ NJU26200 Series Hardware Data Sheet”.
Ver.2008-12-04
-1-
NJU26209
Pin Description
Table 1 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
TEST *
MUTEb *
WDC *
PROC *
VSSIO
VDDIO
SEL
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
VSSIO
VDDIO
RESETb
TEST
TEST
TEST
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
VDDIO
MCK
BCKO
LRO
SDO3
SDO2
SDO1
SDO0
VDDIO
VSSIO
VSS
VDD
I/O
I
I
I
I
I
-
I
-
-
I
I
OD
I
-
-
I
-
-
-
-
O
I
-
-
I
I
I
I
I
I
I
I/O
-
O
O
O
O
O
O
O
-
-
-
-
Function
Audio Data Input ch.3 (LS/RS)
Audio Data Input ch.2 (C/SW)
Audio Data Input ch.1 (L/R)
Audio Data Input ch.0 (L/R)
LR Clock Input
I/O Power Supply +3.3V
Bit Clock Input
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
for test
connect with VSSIO through 3.3-ohm resistance.
Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
Watchdog Clock output pin (Open drain output)
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
I/O Power Supply GND
I/O Power Supply +3.3V
2
Host Interface Selection ‘1’: Serial Interface, ‘0’: I C bus
PLL Power Supply +1.8V
PLL Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
OSC Clock Output
OSC Clock Input (12.288MHz)
I/O Power Supply GND
I/O Power Supply +3.3V
Reset (RESETb=’0’: DSP Reset)
for test (connect to VDDIO)
for test (connect to VSSIO)
for test (connect to VSSIO)
2
2
I C Address (I C mode) / Serial In (4-wire serial mode)
2
2
I C Address (I C mode) / Serial enable (4-wire serial mode)
2
2
I C SCL (I C mode) / Serial clock (4-wire serial mode)
2
2
I C SDA (I C mode) / Serial Out (4-wire serial mode)
I/O Power Supply +3.3V
A/D, D/A clock output (buffer output of a CLK pin)
Bit Clock Output
LR Clock Output
Audio Data Output ch.3 (LM/RM)
Audio Data Output ch.2 (C/SW)
Audio Data Output ch.1 (L/R)
Audio Data Output ch.0 (LS/RS)
I/O Power Supply +3.3V
I/O Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k
Ω
resistance
Ver.2008-12-04
-5-
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