NJU26207
Dolby Volume Decoder
General Description
The NJU26207 is a digital signal processor that provides the function of Dolby Volume.
Dolby Volume solves volume level difference among channels, input sources and etc.
The mix balance is reproduced by high or low volume level.
The applications of NJU26207 are suitable for Digital TV, Front Surround Speaker and
speakers system.
■
Package
Features
-Software
Dolby Volume (512FFT Window / 20Band)
Delay
Master Volume / Balance Control
Sampling Frequency : 32kHz, 44.1kHz, 48kHz
2 Input channels, 2 Output channels
-Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency
: 12.288MHz(Standard), built-in PLL Circuit
Digital Audio Interface
: 4 Input ports / 3 Output ports
Digital Audio Format
: I
2
S 24bit, left-justified, right-justified, BCK : 32fs/64fs
Master / Slave Mode
Microcomputer Interface
I
2
C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
Operating Voltage
: V
DD
= V
DDPLL
= 1.8V
: V
DDIO
= 3.3V
Input Terminal
: +5.0V Input tolerant
Package
: SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26207 is described in the “ NJU26200 Series Hardware Data Sheet”.
NJU26207V
Ver.2008-12-03
-1-
NJU26207
Hardware Block Diagram
AD1/SDIN
AD2/SSb
DSP ARITHMETIC UNIT
SCL/SCK
SERIAL
HOST
INTERFACE
PROGRAM
CONTROL
SERIAL AUDIO
INTERFACE
BCKO
BCKO
LRO
L/Rout
SDA/SDOUT
24-
24-BIT
½
24-BIT
24-
MULTIPLIER
RESETb
MCK
CLK
CLKOUT
ALU
SDO0
SDO0
SDO1
SDO1
SDO2
SDO2
(L+R)/2out
(L+R)/2out
L/R
Monitor L/R
TIMING
GENERATOR
/ PLL
in
ADDRESS GENERATION UNIT
SDI0~3
SDI0~3
BCKI
LRI
PROC
DATA
RAM
FIRMWARE
ROM
General I/O
INTERFACE
MUTEb
SEL
WDC
Fig. 1 NJU26207 Hardware Block Diagram
Function Block Diagram
Delay
L/R(SDI0)
L/R(SDI1)
L/R(SDI2)
L/R(SDI3)
Dolby
Volume
Fig. 2 NJU26207 Function Block Diagram (Firmware)
Output Trimmer
(Master&Balance)
L/R(SDO0)
(L+R)/2(SDO1)
Monitor L/R(SDO2)
-2-
Ver.2008-12-03
NJU26207
Pin Configuration
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
TEST
MUTEb
WDC
PROC
VSSIO
VDDIO
SEL
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NJU26207
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
VSS
VSSIO
VDDIO
SDO0
SDO1
SDO2
TEST
LRO
BCKO
MCK
VDDIO
SDA/SDOUT
SCL/SCK
AD2/SSb
AD1/SDIN
TEST
TEST
TEST
RESETb
VDDIO
VSSIO
SSOP44
Fig. 3 NJU26207 Pin Configuration
Ver.2008-12-03
-3-
NJU26207
Pin Description
Table 1 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
TEST *
MUTEb *
WDC *
PROC *
VSSIO
VDDIO
SEL
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
VSSIO
VDDIO
RESETb
TEST
TEST
TEST
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
VDDIO
MCK
BCKO
LRO
TEST
SDO2
SDO1
SDO0
VDDIO
VSSIO
VSS
VDD
I/O
I
I
I
I
I
-
I
-
-
I
I
OD
I
-
-
I
-
-
-
-
O
I
-
-
I
I
I
I
I
I
I
I/O
-
O
O
O
O
O
O
O
-
-
-
-
Function
Audio Data Input ch.3 (L/R)
Audio Data Input ch.2 (L/R)
Audio Data Input ch.1 (L/R)
Audio Data Input ch.0 (L/R)
LR Clock Input
I/O Power Supply +3.3V
Bit Clock Input
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
for test
connect with VSSIO through 3.3-ohm resistance.
Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
Watchdog Clock output pin (Open drain output)
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
I/O Power Supply GND
I/O Power Supply +3.3V
2
Host Interface Selection ‘1’: Serial Interface, ‘0’: I C bus
PLL Power Supply +1.8V
PLL Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
OSC Clock Output
OSC Clock Input (12.288MHz)
I/O Power Supply GND
I/O Power Supply +3.3V
Reset (RESETb=’0’: DSP Reset)
for test (connect to VDDIO)
for test (connect to VSSIO)
for test (connect to VSSIO)
2
2
I C Address (I C mode) / Serial In (4-wire serial mode)
2
2
I C Address (I C mode) / Serial enable (4-wire serial mode)
2
2
I C SCL (I C mode) / Serial clock (4-wire serial mode)
2
2
I C SDA (I C mode) / Serial Out (4-wire serial mode)
I/O Power Supply +3.3V
A/D, D/A clock output (buffer output of a CLK pin)
Bit Clock Output
LR Clock Output
For test (Non connect)
Audio Data Output ch.2 (Monitor L/R)
Audio Data Output ch.1 ((L+R)/2)
Audio Data Output ch.0 (L/R)
I/O Power Supply +3.3V
I/O Power Supply GND
DSP Core Power Supply GND
DSP Core Power Supply +1.8V
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k
Ω
resistance
-4-
Ver.2008-12-03
NJU26207
The NJU26207 audio interface provides industry serial data formats of I
2
S, MSB-first Left-justified or MSB-first
Right-justified. The NJU26207 audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and three data
outputs, SDO0, SDO1 and SDO2 as shown in table 2 and 3. The input serial data is selected by the firmware
command.
Table 2 Serial Audio Input Pin
Pin No.
Symbol
Description
4
SDI0
Audio Data Input 0 (L/R)
3
SDI1
Audio Data Input 1 (L/R)
2
SDI2
Audio Data Input 2 (L/R)
1
SDI3
Audio Data Input 3 (L/R)
Table 3 Serial Audio Output Pin
Pin No.
Symbol
Description
40
SDO0
Audio Data Output 0 (L/R)
39
SDO1
Audio Data Output 1 ((L/R)/2)
38
SDO2
Audio Data Output 2 (Monitor L/R)
Audio Interface
The NJU26207 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I
2
C bus or
4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a
SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data
transfers, regardless of the chosen communication protocol.
The detail I
2
C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data
Sheet’.
Table 4 Serial Host Interface Pin Descriptions
Pin No.
Symbol
Setting
Low
16
SEL
High
Table 5
Pin No.
29
30
31
32
Host Interface
Host Interface
I C Bus Interface
4-Wire Serial Interface
2
Serial Host Interface Pin Description
Symbol
2
(I C /Serial)
AD1/SDIN
AD2/SSb
SCL/SCK
SDA/SDOUT
2
2
I C bus Interface
4-Wire Serial Interface
Serial data input
Slave select
Serial Clock
Serial data output
(CMOS Output)
I C Address Select Bit1
2
I C Address Select Bit2
Serial Clock
Serial Data Input/Output
(Open Drain output)
2
Note:
When I C Bus is selected, the SDA/SDOUT pin is a bi-directional Open Drain output. This pin, which is assigned
2
for I C Bus, requires a pull-up resistance.
When
4-Wire Serial bus is selected, the SDA/SDOUT pin is CMOS output.
The SDA/SDOUT pin isn’t 5.0V Input tolerant.
Ver.2008-12-03
-5-
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