NCP5623B
Triple Output I
2
C Controlled
RGB LED Driver
The NCP5623B mixed analog circuit is a triple output LED driver
dedicated to the RGB illumination or backlight LCD display.
The built−in DC/DC converter is based on a high efficient charge
pump structure with operating mode 1x and 2x. It provides a 94% peak
efficiency. The tiny package makes the device suitable for room
limited portable applications.
Features
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LLGA12
MU SUFFIX
CASE 513AA
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1
2.7 to 5.5 V Input Voltage Range
RGB Function Fully Supported
Programmable Integrated Gradual Dimming
90 mA Output Current Capability
94% Peak Efficiency
Built−in Short Circuit Protection
Provides Three Independent LED Drives
Support I
2
C Protocol
Embedded OVP / Open Load Protection
This is a Pb−Free Device
PIN ASSIGNMENT
2
GND
LED3
LED2
LED1
AGND
6
(Top View)
7
EXPAD
C1P C1N 11
1
Vbat
VOUT
SCL
IREF
SDA
Typical Applications
MARKING DIAGRAM
1
GVMG
G
GV = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Multicolor Illuminations
Portable Back Light
Digital Cellular Phone Camera Photo Flash
LCD and Key Board Simultaneous Drive
+Vbat
+Vcc
1
mF/6.3
V
C1
GND
MCU
SDA
I2C Port
SCL
7
9
6
GND
GND
GND
Rset
62 k
8
11
CFLY
C2
220 nF
1
C1P
Vbat
SDA
SCL
AGND
IREF
12
C1N 10
Vout
LED3
LED2
LED1
GND
3
D3
4
D2
5
2
GND
D1
1
mF/10
V
GND
ORDERING INFORMATION
Device
NCP5623BMUTBG
Package
Shipping
†
LLGA12 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCP5623B
U1
Figure 1. Typical Multiple White LED Driver
©
Semiconductor Components Industries, LLC, 2015
1
February, 2015 − Rev. 3
Publication Order Number:
NCP5623B/D
NCP5623B
CFLY
220 nF
1
NCP5623B
12
C2
1.0
mF/10
V
1
mF/6.3
V
11
C1
GND
Vbat
AGND
OVER VOLTAGE
6
DIGITAL CONTROL
Vbat
SDA
SCL
7
9
Vbat
PWM LED#1
Rset
62 k
8
PWM LED#2
PWM LED#3
GND LED1
5
GND
CURRENT
MIRRORS GND
2
GND
GND
LED2
4
LED3
3
D3
D2
D1
Vbat
CHARGE PUMP
DC/DC CONVERTER
10
Vout
GND
GND
ANALOG
FUNCTIONS
Figure 2. Simplified Block Diagram
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2
NCP5623B
PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
Name
C1P
GND
LED3
LED2
LED1
AGND
SDA
I
REF
Type
POWER
POWER
INPUT,
POWER
INPUT,
POWER
INPUT,
POWER
ANALOG
GROUND
INPUT,
DIGITAL
INPUT,
ANALOG
Description
One side of the external charge pump capacitor (C
FLY
) is connected to this pin, associated with C1N,
pin 12 (Note 1).
This pin is the GROUND signal for the analog and digital blocks and must be connected to the system
ground.
This pin sinks to ground and monitors the current flowing into the LED3, intended to be used in illu-
mination application (Note 2). The Anode of the associated LED shall be connected to the Vout pin.
This pin sinks to ground and monitors the current flowing into the LED2, intended to be used in illu-
mination application (Note 2). The Anode of the associated LED shall be connected to the Vout pin.
This pin sinks to ground and monitors the current flowing into the LED1, intended to be used in illu-
mination application (Note 2).
This pin copies the Analog Ground and must be connected to the system ground plane.
This pin carries the data provided by the I
2
C protocol. The content of the SDA byte is used to program
the mode of operation and to set up the output current (Note 1).
This pin provides the reference current, based on the internal band−gap voltage reference, to control
the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the high-
est accuracy of the LED biases. An external current mirror can be used to bias this pin to dynamically
set up the I−LED peak current.
In no case shall the voltage at I
REF
pin be forced either higher or lower than the 600 mV provided by
the internal reference.
This pin carries the I
2
C clock to control the Charge Pump converter and to set up the output current.
The SCL clock is associated with the SDA signal.
This pin provides the output voltage supplied by the Charge Pump converter. The Vout pin must be
bypassed by 1
mF
ceramic capacitor located as close as possible to the V
OUT
pin to properly bypass
the output voltage to ground. The circuit shall not operate without such bypass capacitor connected
across the Vout pin and Ground (Note 1).
The output voltage is internally clamped to 5.5 V maximum in the event of a no load situation. On the
other hand, the output current is limited to 40 mA (typical) in the event of a short circuit to ground.
This pin is the input Battery voltage to supply the analog and digital blocks. The pin must be de-
coupled to ground by a 1mF or higher ceramic capacitor (Note 1).
One side of the external charge pump capacitor (C
FLY
) is connected to this pin, associated with C1P,
pin 1 (Note 1)
EXPAD is not physically connected to the die. To optimize power dissipation, EXPAD must be connec-
ted to the system (PCB) power ground plane.
9
10
SCL
VOUT
INPUT,
DIGITAL
OUTPUT,
POWER
11
12
−
VBAT
C1N
EXPAD
INPUT,
POWER
POWER
GROUND
1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI.
2. The peak current is 37 mA for each LED, the total charge pump output DC current being limited to 75 mA.
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NCP5623B
MAXIMUM RATINGS
Symbol
V
BAT
Vout
SDA, SCL,
SHDI2C
ESD
Power Supply (see Figure 3)
Output Power Supply
Digital Input Voltage
Digital Input Current
Human Body Model: R = 1500
W,
C = 100 pF (Note 3)
Machine Model
LLGA12 package
Power Dissipation @ T
A
= +85°C (Note 4)
Thermal Resistance Junction to Case
Thermal Resistance Junction to Air
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Latch−up current maximum rating per JEDEC standard: JESD78.
Rating
Value
−0.3 < Vbat < 7.0
7.0
−0.3 < V < V
BAT
1
2
200
200
51
200
−40 to +85
−40 to +125
+150
−65 to +150
±100
Unit
V
V
V
mA
kV
V
mW
°C/W
°C/W
°C
°C
°C
°C
mA
P
D
R
qJC
R
qJA
T
A
T
J
T
Jmax
T
stg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM)
±2.0
kV per JEDEC standard: JESD22−A114
Machine Model (MM)
±200
V per JEDEC standard: JESD22−A115.
4. The maximum package power dissipation limit must not be exceeded.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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4
NCP5623B
POWER SUPPLY SECTION:
(Typical values are referenced to T
A
= +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
11
10
Symbol
V
bat
I
out
Power Supply
Continuous DC current in the load, PWM = 100%
@ V
f
= 3.4 V, V
bat
= 3.0 V
@ V
f
= 3.4 V, 3.3 V < V
bat
< 5.5 V
Continuous Output Short Circuit Current
2.85 V < Vbat < 4.2 V
Output Voltage Compliance (OVP)
DC/DC Start time (Cout = 1
mF)
3.0 V < Vbat = nominal < 5.5 V
From last acknowledgement bit to full load operation
Stand By Current
3.0 V
≤
V
bat
≤
4.2 V, Iout = 0 mA
Operating Current,
@Iout = 0 mA, 3.0 V
≤
Vbat
≤
4.2 V
RGB Output Current Tolerance
@Vbat = 3.6 V, I
LED
= 10 mA
−25°C < Ta < 85°C
RGB Output Current LED Matching
@Vbat = 3.6 V, I
LED
= 5.0 mA
Charge Pump Operating Frequency
−40°C < Ta < 85°C
Efficiency @ Vbat = 3.6 V
− LED1 to LED3 = 5 mA, Vf = 2.8 V (Total = 15 mA)
− LED1 to LED3 = 20 mA, Vf = 3.2 V (Total = 60 mA)
0.8
4.4
150
Rating
Min
2.7
55
75
45
90
5.7
mA
V
ms
Typ
Max
5.5
Unit
V
mA
10
10
10
Isch
Vout
Tstart
10
10
3,4,5
I
stdb
I
op
I
TOL
0.8
350
±3
1.0
mA
mA
%
3,4,5
I
MATCH
Fpwr
E
PWR
±0.5
1
1.2
%
MHz
%
94.2
92.3
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