NCP5393B
2/3/4-Phase Controller for
CPU Applications
The NCP5393B is a multiphase synchronous buck regulator
controller designed to power the Core and Northbridge of an AMD
microprocessor. The controller has a user configurable two, three, or
four phase regulator for the Core and an independent single phase
regulator to power the microprocessor Northbridge. The NCP5393B
incorporates differential voltage sensing, differential phase current
sensing, optional load−line voltage positioning, and programmable
V
DD
and V
DDNB
offsets to provide accurately regulated power
parallel− and serial−VID AMD processors. Dual−edge multiphase
modulation provides the fastest initial response to dynamic load
events. This reduces system cost by requiring less bulk and ceramic
output capacitance to meet transient regulation specifications.
High performance operational error amplifiers are provided to
simplify compensation of the V
DD
and V
DDNB
regulators. Dynamic
Reference Injection further simplifies loop compensation by
eliminating the need to compromise between response to load
transients and response to VID code changes.
Features
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MARKING
DIAGRAM
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QFN48, 7x7
CASE 485AJ
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NCP5393B
AWLYYWWG
= Assembly Location
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= Work Week
= Pb−Free Package
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Meets AMD’s Hybrid VR Specifications
Up to Four V
DD
Phases
Single−Phase V
DDNB
Controller
Dual−Edge PWM for Fastest Initial Response to Transient Loading
High Performance Operational Error Amplifiers
Internal Soft Start and Slew Rate Limiting
Dynamic Reference Injection (Patent #US07057381)
DAC Range from 12.5 mV to 1.55 V
$0.6%
DAC Accuracy from 0.8 V to 1.55 V
V
DD
and V
DD
Offset Ranges 0 mV
−
800 mV
True Differential Remote Voltage Sense Amplifiers
Phase−to−Phase I
DD
Current Balancing
Differential Current Sense Amplifiers for Each Phase of Each Output
“Lossless” Inductor Current Sensing for V
DD
and V
DDNB
Outputs
Supports Load Lines (Droop) for V
DD
and V
DDNB
Outputs
Oscillator Range of 100 kHz
−
1 MHz
Tracking Over Voltage Protection
Output Inductor DCR−Based Over Current Protection for V
DD
and
V
DDNB
Outputs
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Guaranteed Startup into Precharged Loads
•
Temperature Range: 0°C to 70°C
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This is a Pb−Free Device
Applications
ORDERING INFORMATION
Device
NCP5393BMNR2G
Package
QFN48
(Pb−Free)
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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Desktop Processors
•
Server Processors
•
High−End Notebook PCs
©
Semiconductor Components Industries, LLC, 2010
May, 2010
−
Rev. 2
1
Publication Order Number:
NCP5393B/D
NCP5393B
NCP5393B PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
Symbol
VCCA
GND
COMP
FB
DROOP
VS+
VS−
OFFSET
DIFFOUT
VFIX
Description
5 V supply pin for the NCP5393B. The V
CC
bypassing capacitance must be connected between this
pin and GND (preferably returned to the package flag).
Small−signal power supply return. This pin should be tied directly to the package flag (exposed pad).
Output of the voltage error amplifier for the V
DD
regulator.
Voltage error amplifier inverting input for the V
DD
regulator.
Voltage output signal proportional to total current drawn from the V
DD
regulator. Used when load line
operation (“droop”) is desired.
Non−inverting input to the differential remote sense amplifier for the V
DD
regulator.
Inverting input to the differential remote sense amplifier for the V
DD
regulator.
Input for offset voltage to be added to the V
DD
DAC’s output voltage. Ground this pin for zero V
DD
offset.
Output of the differential remote sense amplifier for the V
DD
regulator.
When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded
as a two−bit DAC code, which controls the V
DD
and VDDNB outputs. Internally pulled high by 5
mA
to
V
CC
UVLO monitor input for the 12 V power rail.
Determines number of phases operating in PSI_L mode. Phase shed count is locked upon ENABLE
assertion. After soft−start, becomes power saving control in PVID mode. Low = phase shed
operation, High = normal operation.
Non−inverting input to current sense amplifier #1 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #1 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
Non−inverting input to current sense amplifier #2 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #2 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
Non−inverting input to current sense amplifier #3 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #3 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
Non−inverting input to current sense amplifier #4 for the V
DD
regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #4 for the V
DD
regulator. See Table: “Pin Connections vs.
Phase Count”
Overcurrent shutdown threshold for V
DD
and VDDNB. A resistor divider from ROSC to GND is
typically used to develop an appropriate voltage on ILIM.
5 V supply pin. Tie this pin to VCCA (Pin 1).
Non−inverting input to the current sense amplifier for the VDDNB regulator
Inverting input to the current sense amplifier for the VDDNB regulator
Parallel Voltage ID DAC Input 4. Not used in SVI mode.
Parallel Voltage ID DAC Input 5. Not used in SVI mode.
A resistance from this pin to ground programs the V
DD
and VDDNB oscillator frequencies. This pin
supplies a trimmed output voltage of 2 V.
Output of the differential remote sense amplifier for the VDDNB regulator.
Input for offset voltage to be added to the VDDNB DAC’s output voltage. Ground this pin for zero
VDDNB offset.
Inverting input to the differential remote sense amplifier for the VDDNB regulator.
Non−inverting input to the differential remote sense amplifier for the VDDNB regulator.
11
12
12VMON
PSI_L
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CS1
CS1N
CS2
CS2N
CS3
CS3N
CS4
CS4N
ILIM
VCCB
NB_CS
NB_CSN
VID4
VID5
ROSC
NB_DIFFOUT
NB_OFFSET
NB_VS−
NB_VS+
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