ADP3212, NCP3218,
NCP3218G
7-Bit, Programmable,
3-Phase, Mobile CPU
Synchronous Buck Controller
The APD3212/NCP3218/NCP3218G is a highly efficient,
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multi−phase, synchronous buck switching regulator controller. With
its integrated drivers, the APD3212/NCP3218/NCP3218G is
optimized for converting the notebook battery voltage into the core
supply voltage required by high performance Intel processors. An
internal 7−bit DAC is used to read a VID code directly from the
1 48
processor and to set the CPU core voltage to a value within the range
1 48
QFN48
QFN48
of 0.3 V to 1.5 V. The APD3212/NCP3218/NCP3218G is
CASE 485AJ
CASE 485BA
programmable for 1−, 2−, or 3−phase operation. The output signals
ensure interleaved 2− or 3−phase operation.
MARKING DIAGRAM
The APD3212/NCP3218/NCP3218G uses a multimode architecture
1
run at a programmable switching frequency and optimized for
xxx = Specific Device Code
efficiency depending on the output current requirement. The
(ADP3212 or NCP3218/G)
xxP321x
APD3212/NCP3218/NCP3218G switches between single− and
A
= Assembly Location
AWLYYWWG WL = Wafer Lot
multi−phase operation to maximize efficiency with all load conditions.
YY = Year
The chip includes a programmable load line slope function to adjust the
WW = Work Week
output voltage as a function of the load current so that the core voltage is
G
= Pb−Free Package
always optimally positioned for a load transient. The APD3212/
NCP3218/NCP3218G also provides accurate and reliable short−circuit
ORDERING INFORMATION
protection, adjustable current limiting, and a delayed power−good
See detailed ordering and shipping information in the package
output. The IC supports On−The−Fly (OTF) output voltage changes
dimensions section on page 33 of this data sheet.
requested by the CPU.
The APD3212/NCP3218/NCP3218G are specified over
•
Active Current Balancing Between Output Phases
the extended commercial temperature range of
−40°C
to
•
Independent Current Limit and Load Line Setting
100°C. The ADP3212 is available in a 48−lead QFN 7x7mm
Inputs for Additional Design Flexibility
0.5mm pitch package. The NCP3218/NCP3218G is
•
Built−In Power−Good Blanking Supports Voltage
available in a 48−lead QFN 6x6mm 0.4mm pitch package.
Identification (VID) On−The−Fly (OTF) Transients
ADP3212/NCP3218 has 1.1 V Vboot Voltage, while
•
7−Bit, Digitally Programmable DAC with 0.3 V to
NCP3218G has 987.5 mV Vboot Voltage. Except for the
1.5 V Output
packages and Vboot Voltages, the APD3212/NCP3218/
•
Short−Circuit Protection with Programmable Latchoff
NCP3218G are identical. APD3212/NCP3218/NCP3218G
Delay
are Halogen−Free, Pb−Free and RoHS compliant.
•
Clock Enable Output Delays the CPU Clock Until the
Features
Core Voltage is Stable
•
Single−Chip Solution
•
Output Power or Current Monitor Options
•
Fully Compatible with the Intel
®
IMVP−6.5t
•
48−Lead QFN 7x7mm (ADP3212), 48−Lead QFN
Specifications
6x6mm (NCP3218/NCP3218G)
•
Selectable 1−, 2−, or 3−Phase Operation with Up to 1
•
Vboot = 1.1 V (ADP3212/NCP3218)
MHz per Phase Switching Frequency
Vboot = 987.5 mV (NCP3218G)
•
Phase 1 and Phase 2 Integrated MOSFET Drivers
•
These are Pb−Free Devices
•
Input Voltage Range of 3.3 V to 22 V
•
Fully RoHS Compliant
•
Guaranteed
±8
mV Worst−Case Differentially Sensed
Applications
Core Voltage Error Over Temperature
•
Notebook Power Supplies for Next−Generation Intel
•
Automatic Power−Saving Mode Maximizes Efficiency
Processors
with Light Load During Deeper Sleep Operation
©
Semiconductor Components Industries, LLC, 2012
August, 2012
−
Rev. 4
1
Publication Order Number:
ADP3212/D
ADP3212, NCP3218, NCP3218G
PIN ASSIGNMENT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI
DPRSLP
PH0
PH1
VCC
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
TRDET
VARFREQ
VRTT
TTSNS
GND
1
ADP3212
NCP3218
(top view)
BST1
DRVH1
SW1
SWFB1
PVCC
DRVL1
PGND
DRVL2
SWFB2
SW2
DRVH2
BST2
GND
VCC EN
UVLO
Shutdown
and Bias
VEA
−
+
CSREF
−
+
IREF
RPM
RT
RAMP
LLINE
CSREF
CSSUM
CSCOMP
ILIM
OD3
PWM3
SWFB3
RPM RT RAMP VARFREQ
BST1
Oscillator
Current
Balancing
Circuit
OVP
Driver
Logic
DRVH1
SW1
PVCC
DRVL1
PGND
BST2
DRVH2
SW2
PVCC
Number of
Phases
OCP
Shutdown
Delay
Current
Limit
Circuit
Soft
Transient
Delay
CLKEN
Start Up
Delay
Delay
Disable
Thermal
Throttle
Control
Soft Start
REF
DRVL2
PGND
OD3
PWM3
PSI and
DPRSLP
Logic
Current
Current
Monitor
Monitor
+
−
PSI
DPRSLP
IMON
CSREF
CSSUM
CSCOMP
ILIM
TTSENSE
VRTT
TRDET
COMP
FB
+
REF
LLINE
SWFB1
SWFB2
SWFB3
PH0
PH1
DAC + 200 mV
CSREF
−
+
−
+
DAC
−
300 mV
PWRGD
Open
Drain
CLKEN
Open
Drain
Precision
Reference
VID
DAC
PWRGD
Start Up
Delay
S
TRDET
Generator
+
S
_
+
1.55 V
PWRGD
CLKEN
FBRTN
DAC
IREF
2
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Figure 1. Functional Block Diagram
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ADP3212, NCP3218, NCP3218G
ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC
, PV
CC1
, PV
CC2
FBRTN, PGND1, PGND2
BST1, BST2, DRVH1, DRVH2
DC
t < 200 ns
BST1 to PV
CC
, BST2 to PV
CC
DC
t < 200 ns
BST1 to SW1, BST2 to SW2
SW1, SW2
DC
t < 200 ns
DRVH1 to SW1, DRVH2 to SW2
DRVL1 to PGND1, DRVL2 to PGND2
DC
t < 200 ns
RAMP (in Shutdown)
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (q
JA
) 2−Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3
to +6.0
−0.3
to +0.3
−0.3
to +28
−0.3
to +33
−0.3
to +22
−0.3
to +28
−0.3
to +6.0
−1.0
to +22
−6.0
to +28
−0.3
to +6.0
−0.3
to +6.0
−5.0
to +6.0
−0.3
to +22
−0.3
to +6.0
−65
to +150
−40
to +100
125
30.5
300
260
Unit
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
TRDET
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and
VRTT low, and pulls CLKEN high.
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to
the external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive
load transients at high frequencies, this circuit optimally positions the maximum and minimum output
voltage into a specified loadline window.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
9
10
VARFREQ
VRTT
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3
ADP3212, NCP3218, NCP3218G
PIN ASSIGNMENT
Pin No.
11
Mnemonic
TTSNS
Description
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected
to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this
pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling
function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.
Analog and Digital Signal Ground.
This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.
RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on
threshold voltage.
Multi−phase Frequency Setting Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device when operating in multi−phase PWM mode threshold of the converter.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets
the slope of the internal PWM stabilizing ramp used for phase−current balancing.
Output Load Line Programming Input. The center point of a resistor divider between CSREF and
CSCOMP is connected to this pin to set the load line slope.
Current Sense Reference Input. This pin must be connected to the common point of the output inductors.
The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop
transient control of the converter output voltage.
Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor
currents to provide total current information.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of
the current−sense amplifier and the positioning loop response time.
Current Limit Setpoint. An external resistor from this pin to CSCOMP sets the current limit threshold of the
converter.
Multi−phase Output Disable Logic Output. This pin is actively pulled low when the APD3212/NCP3218/
NCP3218G enters single−phase mode or during shutdown. Connect this pin to the SD inputs of the
Phase−3 MOSFET drivers.
Logic−Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the
ADP3611.
Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left
open for 1 or 2 phase configuration.
High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage
while the high−side MOSFET is on.
High−Side Gate Drive Output for Phase 2.
Current Return for High−Side Gate Drive for phase 2.
Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left
open for 1 phase configuration.
Low−Side Gate Drive Output for Phase 2.
Low−Side Driver Power Ground
Low−Side Gate Drive Output for Phase 1.
Power Supply Input/Output of Low−Side Gate Drivers.
Current Balance Input for phase 1. Input for measuring the current level in phase 1.
Current Return For High−Side Gate Drive for phase 1.
High−Side Gate Drive Output for Phase 1.
High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage
while the high−side MOSFET is on.
Power Supply Input/Output of the Controller.
Phase Number Configuration Input. Connect to VCC for 3 phase configuration.
Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for
multi−phase configuration.
Deeper Sleep Control Input.
Power State Indicator Input. Pulling this pin to GND forces the APD3212/NCP3218/NCP3218G to operate
in single−phase mode.
Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB
regulation voltage from 0.3 V to 1.5 V (see Table 3).
12
13
14
15
16
17
18
GND
IREF
RPM
RT
RAMP
LLINE
CSREF
19
20
21
22
CSSUM
CSCOMP
ILIM
OD3
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42 to
48
PWM3
SWFB3
BST2
DRVH2
SW2
SWFB2
DRVL2
PGND
DRVL1
PVCC
SWFB1
SW1
DRVH1
BST1
VCC
PH1
PH0
DPRSLP
PSI
VID6 to VID0
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4
ADP3212, NCP3218, NCP3218G
ELECTRICAL CHARACTERISTICS
V
CC
= PV
CC
= 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V
VID
= V
DAC
= 1.2000 V, T
A
=
−40°C
to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOLTAGE CONTROL
VOLTAGE ERROR AMPLIFIER (VEAMP)
FB, LLINE Voltage Range (Note 2)
FB, LLINE Offset Voltage (Note 2)
LLINE Bias Current
FB Bias Current
LLINE Positioning Accuracy
COMP Voltage Range (Note 2)
COMP Current
V
FB
, V
LLINE
V
OSVEA
I
LLINE
I
FB
V
FB
−
V
VID
V
COMP
I
COMP
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
C
COMP
= 10 pF, CSREF = VDAC,
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
Non−inverting unit gain configuration,
R
FB
= 1 kW
See VID table
V
FB
−
V
VID
Measured on FB (includes offset),
relative to V
VID
V
VID
= 1.2000 V to 1.5000 V,
T =
−40°C
to 100°C
V
VID
= 0.3000 V to 1.1875 V,
T =
−40°C
to 100°C
0
Measured on FB relative to V
VID
,
LLINE forced 80 mV below CSREF
Relative to CSREF = VDAC
Relative to CSREF = VDAC
−200
−0.5
−100
−1.0
−77.5
0.85
−0.75
6
−80
+200
+0.5
+100
+1.0
−82.5
4.0
mV
mV
nA
mA
mV
V
mA
COMP Slew Rate
SR
COMP
V/ms
15
−20
20
MHz
Gain Bandwidth (Note 2)
VID DAC VOLTAGE REFERENCE
VDAC Voltage Range (Note 2)
VDAC Accuracy
GBW
1.5
V
mV
−8.5
−7.5
−1.0
+8.5
+7.5
+1.0
0.02
1.100
987.5
200
1.4
60
0.0625
0.25
1.0
0.4
−90
−200
mA
LSB
%
V
mV
ms
ms
ms
LSB/ms
VDAC Differential Non−linearity
(Note 2)
VDAC Line Regulation
VDAC Boot Voltage
(ADP3212, NCP3218)
VDAC Boot Voltage (NCP3218G)
Soft−Start Delay (Note 2)
Soft−Start Time
Boot Delay
VDAC Slew Rate (Note 2)
ΔV
FB
V
BOOTFB
V
BOOTFB
t
DSS
t
SS
t
BOOT
VCC = 4.75 V to 5.25 V
Measured during boot delay period
Measured during boot delay period
Measured from EN pos edge to
FB = 50 mV
Measured from FB = 50 mV to FB
settles to 1.1 V within 5%
Measured from FB settling to 1.1 V
within 5% to CLKEN neg edge
Soft−Start
Non−LSB VID step, DPRSLP = H,
Slow C4 Entry/Exit
Non−LSB VID step, DPRSLP = L,
Fast C4 Exit
LSB VID step, DVID transition
I
FBRTN
FBRTN Current
VOLTAGE MONITORING and PROTECTION
POWER GOOD
CSREF Undervoltage Threshold
CSREF Overvoltage Threshold
CSREF Crowbar Voltage
Threshold
1.
2.
3.
4.
V
UVCSREF
V
OVCSREF
V
CBCSREF
Relative to nominal VDAC voltage
Relative to nominal VDAC voltage
Relative to FBRTN, V
VID
> 1.1 V
Relative to FBRTN, V
VID
≤
1.1 V
−240
150
1.5
1.3
−300
200
1.55
1.35
−360
250
1.6
1.4
mV
mV
V
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization, not production tested.
Based on bench characterization data.
Timing is referenced to the 90% and 10% points, unless otherwise noted.
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